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MANUAL.md

@@ -5326,6 +5326,67 @@ The most relevant clauses of IEEE1800-2017 are:
 - 12.7 Loop statements
 
 
+
+* * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * *
+
+## Syntax Rule: `unpacked_array`
+
+### Hint
+
+Avoid using unpacked arrays in variable declarations.
+
+### Reason
+
+Unpacked arrays can lead to issues during synthesis.
+
+### Pass Example (1 of 2)
+```systemverilog
+module M;
+
+logic [31:0] a;
+
+endmodule
+```
+
+### Pass Example (2 of 2)
+```systemverilog
+module M;
+
+logic [7:0][3:0] b;
+
+endmodule
+```
+
+### Fail Example (1 of 2)
+```systemverilog
+module M;
+
+logic a [7:0];
+
+endmodule;
+```
+
+### Fail Example (2 of 2)
+```systemverilog
+module M;
+
+logic [31:0] b [0:7];
+
+endmodule;
+```
+
+### Explanation
+
+This rule forbids unpacked array declarations.
+
+Unpacked arrays are not guaranteed to be represented as contiguous memory, and can cause issues with synthesis tools, especially with how multidimensional arrays are synthesized. For example, a synthesis tool might synthesize out unused memory locations of an unpacked array which is not the intended behavior.
+
+Additionally, packed arrays allow the user to intuitively index and slice the array and apply bitwise operations.
+
+The most relevant clauses of IEEE1800-2017 are:
+- 7.4 Packed and unpacked arrays
+
+
 # Naming Convention Syntax Rules
 
 Rules for checking against naming conventions are named with either the suffix