Merge pull request #975 from diffblue/default_disable1

SVA: KNOWNBUG test for `default disable iff`
diffblue · Feb 9, 2025 · cc81eba · cc81eba
2 parents a038c3c + 908ddc7
commit cc81eba
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diff --git a/regression/verilog/SVA/default_disable1.desc b/regression/verilog/SVA/default_disable1.desc
@@ -0,0 +1,8 @@
+KNOWNBUG
+default_disable1.sv
+
+^EXIT=10$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
diff --git a/regression/verilog/SVA/default_disable1.sv b/regression/verilog/SVA/default_disable1.sv
@@ -0,0 +1,7 @@
+module main(input clock, reset);
+
+  default clocking cb @(posedge clk);
+  endclocking
+  default disable iff (!reset);
+
+endmodule