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Add default cases
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Signed-off-by: Matthew Hall <[email protected]>
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matthewhall2 committed Sep 23, 2024
1 parent 1c2a3cb commit 7dd1f72
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Showing 3 changed files with 11 additions and 1 deletion.
2 changes: 1 addition & 1 deletion compiler/z/codegen/BinaryEvaluator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -1226,7 +1226,7 @@ genericLongShiftSingle(TR::Node * node, TR::CodeGenerator * cg, TR::InstOpCode::
}
else if (firstChild->getOpCodeValue() == TR::land && firstChild->getReferenceCount() == 1)
{
trgReg = TR::TreeEvaluator::tryToReplaceShiftLandWithRotateInstruction(firstChild, cg, value, node->getOpCodeValue() == TR::lshl);
trgReg = TR::TreeEvaluator::tryToReplaceShiftLandWithRotateInstruction(firstChild, cg, value, node->getOpCodeValue() == TR::lshl);
if (NULL != trgReg)
{
node->setRegister(trgReg);
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2 changes: 2 additions & 0 deletions compiler/z/codegen/ControlFlowEvaluator.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -743,6 +743,8 @@ OMR::Z::TreeEvaluator::returnEvaluator(TR::Node * node, TR::CodeGenerator * cg)
case TR::Return:
comp->setReturnInfo(TR_VoidReturn);
break;
default:
break;
}

TR::Instruction * inst = generateS390PseudoInstruction(cg, TR::InstOpCode::retn, node, dependencies);
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8 changes: 8 additions & 0 deletions compiler/z/codegen/OMRMachine.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -153,6 +153,8 @@ OMR::Z::Machine::registerCopy(TR::CodeGenerator* cg,
case TR_VRF:
cursor = generateVRRaInstruction(cg, TR::InstOpCode::VLR, node, targetReg, sourceReg, precedingInstruction);
break;
default:
break;
}

cg->traceRAInstruction(cursor);
Expand Down Expand Up @@ -2474,6 +2476,8 @@ OMR::Z::Machine::freeBestRegister(TR::Instruction * currentInstruction, TR::Regi
maskI = first = TR::RealRegister::FirstVRF;
last = TR::RealRegister::LastVRF;
break;
default:
break;
}

int32_t preference = 0, pref_favored = 0;
Expand Down Expand Up @@ -2669,6 +2673,8 @@ OMR::Z::Machine::spillRegister(TR::Instruction * currentInstruction, TR::Registe

opCode = TR::InstOpCode::VL;
break;
default:
break;
}

TR::MemoryReference * tempMR = generateS390MemoryReference(currentNode, location->getSymbolReference(), self()->cg());
Expand Down Expand Up @@ -2842,6 +2848,8 @@ OMR::Z::Machine::reverseSpillState(TR::Instruction *currentInstruction,
dataSize = 16;
opCode = TR::InstOpCode::VST;
break;
default:
break;
}

if (self()->cg()->isOutOfLineColdPath())
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