Parse with DOM and set Attributes to File/FileSet

pyEDAA/ProjectModel/Xilinx/Vivado.py

@@ -30,13 +30,46 @@
 # ============================================================================
 #
 from pathlib import Path
+from typing import Iterable
 
-from lxml import etree
+from xml.dom import minidom, Node
 from pyVHDLModel import VHDLVersion
 from pydecor import export
 
-from pyEDAA.ProjectModel import ConstraintFile, ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, \
-	VHDLSourceFile, File, VerilogSourceFile
+from pyEDAA.ProjectModel import ProjectFile, XMLFile, XMLContent, SDCContent, Project, FileSet, File, Attribute
+from pyEDAA.ProjectModel import File as Model_File
+from pyEDAA.ProjectModel import ConstraintFile as Model_ConstraintFile
+from pyEDAA.ProjectModel import VerilogSourceFile as Model_VerilogSourceFile
+from pyEDAA.ProjectModel import VHDLSourceFile as Model_VHDLSourceFile
+
+
+@export
+class UsedInAttribute(Attribute):
+	KEY = "UsedIn"
+	VALUE_TYPE = Iterable[str]
+
+	def __init__(self):
+		super().__init__()
+
+
+@export
+class File(Model_File):
+	pass
+
+
+@export
+class ConstraintFile(Model_ConstraintFile):
+	pass
+
+
+@export
+class VerilogSourceFile(Model_VerilogSourceFile):
+	pass
+
+
+@export
+class VHDLSourceFile(Model_VHDLSourceFile):
+	pass
 
 
 @export
@@ -54,33 +87,33 @@ def Parse(self):
 			raise Exception(f"Vivado project file '{self._path!s}' not found.") from FileNotFoundError(f"File '{self._path!s}' not found.")
 
 		try:
-			with self._path.open(encoding="utf-8") as fileHandle:
-				content = fileHandle.read()
-				content = bytes(bytearray(content, encoding="utf-8"))
-		except OSError as ex:
+			root = minidom.parse(str(self._path)).documentElement
+		except Exception as ex:
 			raise Exception(f"Couldn't open '{self._path!s}'.") from ex
 
-		XMLParser = etree.XMLParser(remove_blank_text=True, encoding="utf-8")
-		root = etree.XML(content, XMLParser)
-
 		self._xprProject = Project(self._path.stem, rootDirectory=self._path.parent)
 		self._ParseRootElement(root)
 
 	def _ParseRootElement(self, root):
-		filesetsNode = root.find("FileSets")
-		for filesetNode in filesetsNode:
-			self._ParseFileSet(filesetNode)
+		for rootNode in root.childNodes:
+			if rootNode.nodeName == "FileSets":
+				for fileSetsNode in rootNode.childNodes:
+					if fileSetsNode.nodeType == Node.ELEMENT_NODE and fileSetsNode.tagName == "FileSet":
+						self._ParseFileSet(fileSetsNode)
 
 	def _ParseFileSet(self, filesetNode):
-		filesetName = filesetNode.get("Name")
+		filesetName = filesetNode.getAttribute("Name")
 		fileset = FileSet(filesetName, design=self._xprProject.DefaultDesign)
 
-		for fileNode in filesetNode:
-			if fileNode.tag == "File":
-				self._ParseFile(fileNode, fileset)
+		for fileNode in filesetNode.childNodes:
+			if fileNode.nodeType == Node.ELEMENT_NODE:
+				if fileNode.tagName == "File":
+					self._ParseFile(fileNode, fileset)
+				elif fileNode.nodeType == Node.ELEMENT_NODE and fileNode.tagName == "Config":
+					self._ParseFileSetConfig(fileNode, fileset)
 
 	def _ParseFile(self, fileNode, fileset):
-		croppedPath = fileNode.get("Path").replace("$PPRDIR/", "")
+		croppedPath = fileNode.getAttribute("Path").replace("$PPRDIR/", "")
 		filePath = Path(croppedPath)
 		if filePath.suffix in (".vhd", ".vhdl"):
 			self._ParseVHDLFile(fileNode, filePath, fileset)
@@ -96,12 +129,24 @@ def _ParseFile(self, fileNode, fileset):
 	def _ParseVHDLFile(self, fileNode, path, fileset):
 		vhdlFile = VHDLSourceFile(path)
 		fileset.AddFile(vhdlFile)
+		usedInAttr = []
 
-		if fileNode[0].tag == "FileInfo":
-			if fileNode[0].get("SFType") == "VHDL2008":
-				vhdlFile.VHDLVersion = VHDLVersion.VHDL2008
-			else:
-				vhdlFile.VHDLVersion = VHDLVersion.VHDL93
+		for childNode in fileNode.childNodes:
+			if childNode.nodeType == Node.ELEMENT_NODE and childNode.tagName == "FileInfo":
+				if childNode.getAttribute("SFType") == "VHDL2008":
+					vhdlFile.VHDLVersion = VHDLVersion.VHDL2008
+				else:
+					vhdlFile.VHDLVersion = VHDLVersion.VHDL93
+
+				for fileAttribute in childNode.childNodes:
+					if fileAttribute.nodeType == Node.ELEMENT_NODE and fileAttribute.tagName == "Attr":
+						if fileAttribute.getAttribute("Name") == "Library":
+							libraryName = fileAttribute.getAttribute("Val")
+							vhdlFile.VHDLLibrary = fileset.GetOrCreateVHDLLibrary(libraryName)
+						elif fileAttribute.getAttribute("Val") == "UsedIn":
+							usedInAttr.append(fileAttribute.getAttribute("Val"))
+
+		vhdlFile[UsedInAttribute] = usedInAttr
 
 	def _ParseDefaultFile(self, _, path, fileset):
 		File(path, fileSet=fileset)
@@ -115,6 +160,12 @@ def _ParseVerilogFile(self, _, path, fileset):
 	def _ParseXCIFile(self, _, path, fileset):
 		IPCoreInstantiationFile(path, fileSet=fileset)
 
+	def _ParseFileSetConfig(self, fileNode, fileset):
+		for option in fileNode.childNodes:
+			if option.nodeType == Node.ELEMENT_NODE and option.tagName == "Option":
+				if option.getAttribute("Name") == "TopModule":
+					fileset.TopLevel = option.getAttribute("Val")
+
 
 @export
 class XDCConstraintFile(ConstraintFile, SDCContent):