支持PCIE 3 PHY拆分配置 / Support PCIe 3 PHY bifurcation

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.c

@@ -122,7 +122,7 @@ AcpiDsdtFixupStatus (
   } DevStatus[] = {
     { "\\_SB.PCI0._STA", FixedPcdGetBool (PcdPcie30Supported) &&
                          PcdGet32 (PcdPcie30State) == PCIE30_STATE_ENABLED },
-    { "\\_SB.PCI1._STA", FALSE }, // not supported yet
+    { "\\_SB.PCI1._STA", PcdGet8 (PcdPcie30PhyMode) != PCIE30_PHY_MODE_AGGREGATION },
     { "\\_SB.PCI2._STA", PcdGet32 (PcdComboPhy1Mode) == COMBO_PHY_MODE_PCIE },
     { "\\_SB.PCI3._STA", PcdGet32 (PcdComboPhy2Mode) == COMBO_PHY_MODE_PCIE },
     { "\\_SB.PCI4._STA", PcdGet32 (PcdComboPhy0Mode) == COMBO_PHY_MODE_PCIE },

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/AcpiPlatformDxe/AcpiPlatformDxe.inf

@@ -55,6 +55,7 @@
   gRK3588TokenSpaceGuid.PcdComboPhy2Mode
   gRK3588TokenSpaceGuid.PcdPcie30Supported
   gRK3588TokenSpaceGuid.PcdPcie30State
+  gRK3588TokenSpaceGuid.PcdPcie30PhyMode
   gRK3588TokenSpaceGuid.PcdPcieEcamCompliantSegmentsMask
   gRockchipTokenSpaceGuid.PcdRkSdmmcBaseAddress
 

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.c

@@ -604,6 +604,10 @@ FdtFixupPcie3Devices (
 
   FdtEnableNode (Fdt, "/pcie@fe150000",
               PcdGet32 (PcdPcie30State) == PCIE30_STATE_ENABLED);
+  if (PcdGet8 (PcdPcie30PhyMode) != PCIE30_PHY_MODE_AGGREGATION) {
+    FdtEnableNode (Fdt, "/pcie@fe160000",
+                PcdGet32 (PcdPcie30State) == PCIE30_STATE_ENABLED);
+  }
 }
 
 STATIC

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/FdtPlatformDxe/FdtPlatformDxe.inf

@@ -56,6 +56,7 @@
   gRK3588TokenSpaceGuid.PcdComboPhy2Mode
   gRK3588TokenSpaceGuid.PcdPcie30Supported
   gRK3588TokenSpaceGuid.PcdPcie30State
+  gRK3588TokenSpaceGuid.PcdPcie30PhyMode
 
 [Depex]
   gRockchipPlatformConfigAppliedProtocolGuid

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/PciExpress30.c

@@ -30,6 +30,8 @@ SetupPcie30Variables (
 {
   UINTN      Size;
   UINT32     Var32;
+  UINT8      Var8;
+
   EFI_STATUS Status;
 
   Size = sizeof (UINT32);
@@ -41,4 +43,14 @@ SetupPcie30Variables (
     Status = PcdSet32S (PcdPcie30State, FixedPcdGet32 (PcdPcie30Supported));
     ASSERT_EFI_ERROR (Status);
   }
+
+  Size = sizeof (UINT8);
+
+  Status = gRT->GetVariable (L"Pcie30PhyMode",
+                            &gRK3588DxeFormSetGuid,
+                            NULL, &Size, &Var8);
+  if (EFI_ERROR (Status) || !FixedPcdGetBool (PcdPcie30Supported)) {
+    Status = PcdSet8S (PcdPcie30PhyMode, FixedPcdGet8 (PcdPcie30PhyModeDefault));
+    ASSERT_EFI_ERROR (Status);
+  }
 }

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588Dxe.inf

@@ -91,6 +91,8 @@
 
   gRK3588TokenSpaceGuid.PcdPcie30Supported
   gRK3588TokenSpaceGuid.PcdPcie30State
+  gRK3588TokenSpaceGuid.PcdPcie30PhyMode
+  gRK3588TokenSpaceGuid.PcdPcie30PhyModeDefault
 
   gRK3588TokenSpaceGuid.PcdConfigTableMode
   gRK3588TokenSpaceGuid.PcdAcpiPcieEcamCompatModeDefault

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.uni

@@ -122,6 +122,14 @@
 #string STR_PCIE30_STATE_PROMPT                            #language en-US "Support State"
 #string STR_PCIE30_STATE_HELP                              #language en-US "Enable or disable PCIe 3.0 support."
 
+#string STR_PCIE30_PHY_MODE_PROMPT                         #language en-US "PHY Mode"
+#string STR_PCIE30_PHY_MODE_HELP                           #language en-US "Choose PHY Mode\n\nx4:\n    4l -> PCIe3 PHY lane 0123\n    2l -> Not connected\n    1l0 -> Combo PHY #1\n    1l1 -> Combo PHY #2\n    1l2 -> Combo PHY #0\n\nx2 x2:\n    4l -> PCIe3 PHY lane 01\n    2l -> PCIe3 PHY lane 23\n    1l0 -> Combo PHY #1\n    1l1 -> Combo PHY #2\n    1l2 -> Combo PHY #0\n\nx1x1 x2:\n    4l -> PCIe3 PHY lane 0\n    2l -> PCIe3 PHY lane 23\n    1l0 -> PCIe3 PHY lane 1\n    1l1 -> Combo PHY #2\n    1l2 -> Combo PHY #0\n\nx2 x1x1:\n    4l -> PCIe3 PHY lane 01\n    2l -> PCIe3 PHY lane 2\n    1l0 -> Combo PHY #1\n    1l1 -> PCIe3 PHY lane 3\n    1l2 -> Combo PHY #0\n\nx1x1 x1x1:\n    4l -> PCIe3 PHY lane 0\n    2l -> PCIe3 PHY lane 2\n    1l0 -> PCIe3 PHY lane 1\n    1l1 -> PCIe3 PHY lane 3\n    1l2 -> Combo PHY #0\n"
+#string STR_PCIE30_PHY_MODE_AGGREGATION                    #language en-US "x4"
+#string STR_PCIE30_PHY_MODE_NANBNB                         #language en-US "x2 x2"
+#string STR_PCIE30_PHY_MODE_NANBBI                         #language en-US "x1x1 x2"
+#string STR_PCIE30_PHY_MODE_NABINB                         #language en-US "x2 x1x1"
+#string STR_PCIE30_PHY_MODE_NABIBI                         #language en-US "x1x1 x1x1"
+
 /*
  * ACPI / Device Tree configuration
  */

edk2-rockchip/Silicon/Rockchip/RK3588/Drivers/RK3588Dxe/RK3588DxeHii.vfr

@@ -122,6 +122,11 @@ formset
       name  = Pcie30State,
       guid  = RK3588DXE_FORMSET_GUID;
 
+    efivarstore PCIE30_PHY_MODE_VARSTORE_DATA,
+      attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
+      name  = Pcie30PhyMode,
+      guid  = RK3588DXE_FORMSET_GUID;
+
     efivarstore CONFIG_TABLE_MODE_VARSTORE_DATA,
       attribute = EFI_VARIABLE_BOOTSERVICE_ACCESS | EFI_VARIABLE_RUNTIME_ACCESS | EFI_VARIABLE_NON_VOLATILE,
       name  = ConfigTableMode,
@@ -463,6 +468,19 @@ formset
           option text = STRING_TOKEN(STR_DISABLED), value = PCIE30_STATE_DISABLED, flags = 0;
           option text = STRING_TOKEN(STR_ENABLED), value = PCIE30_STATE_ENABLED, flags = 0;
         endoneof;
+
+        /* shoule we move this to single PHY settings form */
+        oneof varid = Pcie30PhyMode.Mode,
+          prompt      = STRING_TOKEN(STR_PCIE30_PHY_MODE_PROMPT),
+          help        = STRING_TOKEN(STR_PCIE30_PHY_MODE_HELP),
+          flags       = NUMERIC_SIZE_1 | INTERACTIVE | RESET_REQUIRED,
+          default     = FixedPcdGet8 (PcdPcie30PhyModeDefault),
+          option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_AGGREGATION), value = PCIE30_PHY_MODE_AGGREGATION, flags = 0;
+          option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_NANBNB), value = PCIE30_PHY_MODE_NANBNB, flags = 0;
+          option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_NANBBI), value = PCIE30_PHY_MODE_NANBBI, flags = 0;
+          option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_NABINB), value = PCIE30_PHY_MODE_NABINB, flags = 0;
+          option text = STRING_TOKEN(STR_PCIE30_PHY_MODE_NABIBI), value = PCIE30_PHY_MODE_NABIBI, flags = 0;
+        endoneof;
     endform;
 #endif
 

edk2-rockchip/Silicon/Rockchip/RK3588/Include/Library/Rk3588Pcie.h

@@ -27,6 +27,10 @@ PciePinmuxInit(
 
 #define NUM_PCIE_CONTROLLER 5
 
+/*
+ * All pcie controllers supports PCIe 3.0
+ * Here we name them using their device tree name in the linux kernel source
+ */
 #define PCIE_SEGMENT_PCIE30X4 0
 #define PCIE_SEGMENT_PCIE30X2 1
 #define PCIE_SEGMENT_PCIE20L0 2

edk2-rockchip/Silicon/Rockchip/RK3588/Include/VarStoreData.h

@@ -45,6 +45,15 @@ typedef struct {
   UINT32 State;
 } PCIE30_STATE_VARSTORE_DATA;
 
+#define PCIE30_PHY_MODE_AGGREGATION                 4
+#define PCIE30_PHY_MODE_NANBNB                      0
+#define PCIE30_PHY_MODE_NANBBI                      1
+#define PCIE30_PHY_MODE_NABINB                      2
+#define PCIE30_PHY_MODE_NABIBI                      3
+typedef struct {
+  UINT8 Mode;
+} PCIE30_PHY_MODE_VARSTORE_DATA;
+
 #define CONFIG_TABLE_MODE_ACPI                      0x00000001
 #define CONFIG_TABLE_MODE_FDT                       0x00000002
 #define CONFIG_TABLE_MODE_ACPI_FDT                  0x00000003

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.c

@@ -17,8 +17,7 @@
 #include <Library/TimerLib.h>
 #include <Library/CruLib.h>
 #include <Library/UefiBootServicesTableLib.h>
-
-#define PHY_MODE_PCIE_AGGREGATION           4 // hardcoded for now
+#include <Library/PcdLib.h>
 
 #define PCIE30_PHY_GRF                      0xfd5b8000
 /* PCIEPHY_GRF */
@@ -64,14 +63,15 @@ Pcie30PhyInit (
     // UINTN Retry;
 
     DEBUG ((DEBUG_INFO, "PCIe30: PHY init\n"));
+    DEBUG ((DEBUG_INFO, "PCIe30: PHY mode %d\n", PcdGet8(PcdPcie30PhyMode)));
 
     // MicroSecondDelay(100000);
 
     /* Disable power domain */
     MmioWrite32(0xFD8D8150, 0x1 << 23 | 0x1 << 21); // PD_PCIE & PD_PHP
 
-    /* Phy mode: Aggregation NBNB */
-    MmioWrite32(GRF_PCIE30_PHY_CON(0), (0x7 << 16) | PHY_MODE_PCIE_AGGREGATION);
+    /* Phy mode: from pcd Pcie30PhyMode */
+    MmioWrite32(GRF_PCIE30_PHY_CON(0), (0x7 << 16) | PcdGet8(PcdPcie30PhyMode));
 
     MmioWrite32(0xFD7C8A00, (0x1 << 10) | (0x1 << 26)); 
 
@@ -114,4 +114,4 @@ Pcie30PhyInit (
 
     DEBUG ((DEBUG_INFO, "PCIe30: PHY init complete\n"));
     return EFI_SUCCESS;
-}
+}

edk2-rockchip/Silicon/Rockchip/RK3588/Library/Pcie30PhyLib/Pcie30PhyLib.inf

@@ -35,4 +35,7 @@
 
 [FixedPcd]
 
+[Pcd]
+  gRK3588TokenSpaceGuid.PcdPcie30PhyMode
+
 [Guids]