regenerated wrappers

efabless · May 9, 2024 · 28bc314 · 28bc314
1 parent af69b9a
commit 28bc314
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Showing 8 changed files with 103 additions and 26 deletions.
diff --git a/EF_I2S.yaml b/EF_I2S.yaml
@@ -16,7 +16,7 @@ info:
     - serial
   bus:
     - generic
-  type": soft
+  type: soft
   status: verified
   cell_count:
     - IP: TBD

diff --git a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v
@@ -1,5 +1,5 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
 	Author: Mohamed Shalan ([email protected])
 
@@ -21,6 +21,83 @@
 
 `timescale			1ns/1ps
 `default_nettype	none
+
+
+
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan ([email protected])
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
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 module EF_I2S_AHBL #( 
 	parameter	
@@ -132,11 +209,11 @@ module EF_I2S_AHBL #(
 	wire [AW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
 
-	reg [0:0]	RX_FIFO_THRESHOLD_REG;
-	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[0 : 0];
+	reg [AW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
 	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
                                         else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
-                                            RX_FIFO_THRESHOLD_REG <= HWDATA[1-1:0];
+                                            RX_FIFO_THRESHOLD_REG <= HWDATA[AW-1:0];
 
 	reg [0:0]	RX_FIFO_FLUSH_REG;
 	assign	fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];

diff --git a/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v b/hdl/rtl/bus_wrappers/EF_I2S_AHBL.v
@@ -1,5 +1,5 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
 	Author: Mohamed Shalan ([email protected])
 
@@ -101,9 +101,9 @@ module EF_I2S_AHBL #(
 	wire [AW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
 
-	reg [0:0]	RX_FIFO_THRESHOLD_REG;
-	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[0 : 0];
-	`AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, 1)
+	reg [AW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+	`AHBL_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
 
 	reg [0:0]	RX_FIFO_FLUSH_REG;
 	assign	fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];

diff --git a/hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v b/hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v
@@ -1,5 +1,5 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
 	Author: Mohamed Shalan ([email protected])
 
@@ -178,11 +178,11 @@ module EF_I2S_APB #(
 	wire [AW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
 
-	reg [0:0]	RX_FIFO_THRESHOLD_REG;
-	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[0 : 0];
+	reg [AW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
 	always @(posedge PCLK or negedge PRESETn) if(~PRESETn) RX_FIFO_THRESHOLD_REG <= 0;
                                         else if(apb_we & (PADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
-                                            RX_FIFO_THRESHOLD_REG <= PWDATA[1-1:0];
+                                            RX_FIFO_THRESHOLD_REG <= PWDATA[AW-1:0];
 
 	reg [0:0]	RX_FIFO_FLUSH_REG;
 	assign	fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];

diff --git a/hdl/rtl/bus_wrappers/EF_I2S_APB.v b/hdl/rtl/bus_wrappers/EF_I2S_APB.v
@@ -1,5 +1,5 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
 	Author: Mohamed Shalan ([email protected])
 
@@ -101,9 +101,9 @@ module EF_I2S_APB #(
 	wire [AW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
 
-	reg [0:0]	RX_FIFO_THRESHOLD_REG;
-	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[0 : 0];
-	`APB_REG(RX_FIFO_THRESHOLD_REG, 0, 1)
+	reg [AW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+	`APB_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
 
 	reg [0:0]	RX_FIFO_FLUSH_REG;
 	assign	fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];

diff --git a/hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v b/hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v
@@ -1,5 +1,5 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
 	Author: Mohamed Shalan ([email protected])
 
@@ -165,9 +165,9 @@ module EF_I2S_WB #(
 	wire [AW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
 
-	reg [0:0]	RX_FIFO_THRESHOLD_REG;
-	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[0 : 0];
-	always @(posedge clk_i or posedge rst_i) if(rst_i) RX_FIFO_THRESHOLD_REG <= 0; else if(wb_we & (adr_i[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET)) RX_FIFO_THRESHOLD_REG <= dat_i[1-1:0];
+	reg [AW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+	always @(posedge clk_i or posedge rst_i) if(rst_i) RX_FIFO_THRESHOLD_REG <= 0; else if(wb_we & (adr_i[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET)) RX_FIFO_THRESHOLD_REG <= dat_i[AW-1:0];
 
 	reg [0:0]	RX_FIFO_FLUSH_REG;
 	assign	fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];

diff --git a/hdl/rtl/bus_wrappers/EF_I2S_WB.v b/hdl/rtl/bus_wrappers/EF_I2S_WB.v
@@ -1,5 +1,5 @@
 /*
-	Copyright 2023 Efabless Corp.
+	Copyright 2024 Efabless Corp.
 
 	Author: Mohamed Shalan ([email protected])
 
@@ -101,9 +101,9 @@ module EF_I2S_WB #(
 	wire [AW-1:0]	RX_FIFO_LEVEL_WIRE;
 	assign	RX_FIFO_LEVEL_WIRE[(AW - 1) : 0] = fifo_level;
 
-	reg [0:0]	RX_FIFO_THRESHOLD_REG;
-	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[0 : 0];
-	`WB_REG(RX_FIFO_THRESHOLD_REG, 0, 1)
+	reg [AW-1:0]	RX_FIFO_THRESHOLD_REG;
+	assign	fifo_level_threshold	=	RX_FIFO_THRESHOLD_REG[(AW - 1) : 0];
+	`WB_REG(RX_FIFO_THRESHOLD_REG, 0, AW)
 
 	reg [0:0]	RX_FIFO_FLUSH_REG;
 	assign	fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];

diff --git a/verify/uvm-python/i2s_ref_model/i2s_ref_model.py b/verify/uvm-python/i2s_ref_model/i2s_ref_model.py
@@ -63,7 +63,7 @@ def write_bus(self, tr):
             return
         if tr.kind == bus_item.WRITE:
             self.regs.write_reg_value(tr.addr, tr.data, force_write=True)
-            uvm_info(self.tag, f"Writing to {tr.addr} {tr.data}", UVM_LOW)
+            uvm_info(self.tag, f"Writing to register 0x{tr.addr:x} {tr.data}", UVM_LOW)
             if tr.addr == self.regs.reg_name_to_address["CFG"]:
                 self.channels = self.regs.read_reg_value("CFG") & 0b11
                 self.left_justified = True if (self.regs.read_reg_value("CFG") >> 3) & 0b1 else False