gl simulation and fix linting error

.gitignore

@@ -54,3 +54,4 @@ dkms.conf
 a.out
 .out
 .vcd
+gl

hdl/rtl/EF_I2S.v

@@ -191,9 +191,9 @@ module EF_I2S #(parameter DW=32, AW=4) (
             sum <= 'b0;
         else if(sample_rdy & |(current_channel & channels))
             if(sum_ctr == 5'b0)
-                sum = sample_value;
+                sum <= sample_value;
             else
-               if(avg_en) sum = sum + sample_value;
+               if(avg_en) sum <= sum + sample_value;
 
     assign avg_flag = avg_en & (sum[31:5] > avg_threshold);
 

verify/uvm-python/Makefile

@@ -10,12 +10,28 @@ RTL_MACROS += "" # Add macros needed
 BUS_TYPE ?= APB
 ifeq ($(BUS_TYPE),APB)
     RTL_MACROS += -DBUS_TYPE_APB
+	DESIGN_NAME = EF_I2S_APB
+    export CLK_MAKEFILE = PCLK
+    export RST_MAKEFILE = PRESETn
 else ifeq ($(BUS_TYPE),AHB)
     RTL_MACROS += -DBUS_TYPE_AHB
+	DESIGN_NAME = EF_I2S_AHBL
+    export CLK_MAKEFILE = HCLK
+    export RST_MAKEFILE = HRESETn
 else ifeq ($(BUS_TYPE),WISHBONE)
     RTL_MACROS += -DBUS_TYPE_WISHBONE
+	DESIGN_NAME = EF_I2S_WB
+    export CLK_MAKEFILE = clk_i
+    export RST_MAKEFILE = rst_i
 endif
 # RTL_MACROS ?= "-DSKIP_WAVE_DUMP"
+## netlist Gen 
+GL_MACROS += -DFUNCTIONAL  $(RTL_MACROS) -DUNIT_DELAY=\#1
+PRE_SYS_FILES = $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES)
+PDK_DIR = $(HOME)/.volare/volare/sky130/versions/bdc9412b3e468c102d01b7cf6337be06ec6e9c9a/sky130A/
+PDK_FILES = $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/primitives.v $(PDK_DIR)/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v # get this from openlane logs in the future 
+POST_SYS_FILES = $(PWD)/top.v $(VIP_FILES) $(PWD)/../../hdl/gl/synthesis/nl/$(DESIGN_NAME).nl.v
+
 YAML_FILE = $(PWD)/../../EF_I2S.yaml
 MAKEFLAGS += --no-print-directory