updates to IP

EF_I2S.yaml

@@ -17,14 +17,14 @@ info:
   bus:
     - generic
   type: soft
-  status: verified
+  maturity: verified
   cell_count:
     - IP: 2433
     - APB: 2716
     - AHBL: 2799
     - WB: 2941
-  width": "0.0"
-  height": "0.0"
+  width: "0.0"
+  height: "0.0"
   technology: n/a
   clock_freq_mhz:
     - IP: 116

hdl/rtl/EF_I2S.pp.v

@@ -208,7 +208,7 @@ module EF_I2S #(parameter DW=32, AW=4) (
         .rdy(sample_rdy)
     );
 
-    aucohl_fifo #(.DW(DW), .AW(AW)) I2SFIFO (
+    fifo #(.DW(DW), .AW(AW)) I2SFIFO (
         .clk(clk),
         .rst_n(rst_n),
         // .clr(fifo_clr),

hdl/rtl/fifo.v

@@ -0,0 +1,118 @@
+/*
+    A FIFO
+    Depth = 2^AW
+    Width = DW
+*/
+module fifo #(parameter DW=8, AW=4)(
+    input   wire            clk,
+    input   wire            rst_n,
+    input   wire            rd,
+    input   wire            wr,
+    input   wire            flush,
+    input   wire [DW-1:0]   wdata,
+    output  wire            empty,
+    output  wire            full,
+    output  wire [DW-1:0]   rdata,
+    output  wire [AW-1:0]   level    
+);
+
+    localparam  DEPTH = 2**AW;
+
+    //Internal Signal declarations
+    reg [DW-1:0]  array_reg [DEPTH-1:0];
+    reg [AW-1:0]  w_ptr_reg;
+    reg [AW-1:0]  w_ptr_next;
+    reg [AW-1:0]  w_ptr_succ;
+    reg [AW-1:0]  r_ptr_reg;
+    reg [AW-1:0]  r_ptr_next;
+    reg [AW-1:0]  r_ptr_succ;
+
+    // Level
+    reg [AW-1:0] level_reg;
+    reg [AW-1:0] level_next;      
+    reg full_reg;
+    reg empty_reg;
+    reg full_next;
+    reg empty_next;
+
+    wire w_en;
+
+    always @ (posedge clk)
+        if(w_en) begin
+            array_reg[w_ptr_reg] <= wdata;
+        end
+
+    assign rdata = array_reg[r_ptr_reg];   
+    assign w_en = wr & ~full_reg;           
+
+    //State Machine
+    always @ (posedge clk, negedge rst_n) begin 
+        if(!rst_n)
+            begin
+                w_ptr_reg <= 'b0;
+                r_ptr_reg <= 'b0;
+                full_reg  <= 1'b0;
+                empty_reg <= 1'b1;
+                level_reg <= 'd0;
+            end
+        else if(flush)
+            begin
+                w_ptr_reg <= 'b0;
+                r_ptr_reg <= 'b0;
+                full_reg  <= 1'b0;
+                empty_reg <= 1'b1;
+                level_reg <= 'd0;
+            end
+        else
+            begin
+                w_ptr_reg <= w_ptr_next;
+                r_ptr_reg <= r_ptr_next;
+                full_reg  <= full_next;
+                empty_reg <= empty_next;
+                level_reg <= level_next;
+            end
+    end
+
+    //Next State Logic
+    always @* begin
+        w_ptr_succ  =   w_ptr_reg + 1;
+        r_ptr_succ  =   r_ptr_reg + 1;
+        w_ptr_next  =   w_ptr_reg;
+        r_ptr_next  =   r_ptr_reg;
+        full_next   =   full_reg;
+        empty_next  =   empty_reg;
+        level_next  =   level_reg;
+
+        case({w_en,rd})
+            //2'b00: nop
+            2'b01: 
+                if(~empty_reg) begin
+                    r_ptr_next = r_ptr_succ;
+                    full_next = 1'b0;
+                    level_next = level_reg - 1;
+                    if (r_ptr_succ == w_ptr_reg)
+                        empty_next = 1'b1;
+                end
+
+            2'b10: 
+                if(~full_reg) begin
+                    w_ptr_next = w_ptr_succ;
+                    empty_next = 1'b0;
+                    level_next = level_reg + 1;
+                    if (w_ptr_succ == r_ptr_reg)
+                        full_next = 1'b1;
+                end
+
+            2'b11: begin
+                w_ptr_next = w_ptr_succ;
+                r_ptr_next = r_ptr_succ;
+            end
+        endcase
+    end
+
+    //Set Full and Empty
+    assign full = full_reg;
+    assign empty = empty_reg;
+    assign level = level_reg;
+
+endmodule

verify/uvm-python/Makefile

@@ -2,9 +2,9 @@ PLUSARGS += "+UVM_VERBOSITY=UVM_MEDUIM"
 TOPLEVEL := top
 MODULE   ?= top_module
 PDK_FILES ?= /home/nouran/PDK_cheetah_v3/sky130A/libs.ref/sky130_fd_sc_hd/verilog/primitives.v /home/nouran/PDK_cheetah_v3/sky130A/libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v
-AHB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_I2S_AHBL.pp.v
-APB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_I2S_APB.pp.v
-WB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrappers/EF_I2S_WB.pp.v 
+AHB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrapper/EF_I2S_AHBL.pp.v
+APB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrapper/EF_I2S_APB.pp.v
+WB_FILES ?=$(PWD)/../../hdl/rtl/bus_wrapper/EF_I2S_WB.pp.v 
 HDL_FILES ?= $(PWD)/IP_Utilities/rtl/aucohl_lib.v $(PWD)/../../hdl/rtl/EF_I2S.v
 VERILOG_SOURCES ?=  $(PWD)/top.v $(AHB_FILES) $(APB_FILES) $(WB_FILES) $(HDL_FILES) $(PDK_FILES)
 RTL_MACROS += -DUSE_POWER_PINS -DFUNCTIONAL -DUNIT_DELAY=\#1  # Add macros needed