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added yaml file and generated documentation
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NouranAbdelaziz committed May 8, 2024
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139 changes: 139 additions & 0 deletions EF_QSPI_FLASH_WRITER.yaml
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---
info:
name: EF_QSPI_FLASH_WRITER
description: A Quad SPI Flash Writer used to program flash. It can be used along
with flash controller to program the flash then read from it.
repo: github.com/efabless/EF_QSPI_FLASH_WRITER
owner: Efabless Corp.
license: Apache 2.0
author: Mohamed Shalan
email: [email protected]
version: v1.0.0
date: 8-05-2024
category: digital
tags:
- memory
- flash
- qspi
bus:
- AHBL
type: soft
status: verified
cell_count:
- IP: N/A
- AHBL: TBD
width: "0.0"
height: "0.0"
technology: n/a
clock_freq_mhz:
- IP: N/A
- AHBL: TBD
digital_supply_voltage: n/a
analog_supply_voltage: n/a
irq_reg_offset: 65280
fifo_reg_offset: 65024
external_interface:
- name: fr_sck
port: fr_sck
width: 1
direction: input
description: spi clock coming from flash reader
- name: fr_ce_n
port: fr_ce_n
width: 1
direction: input
description: spi slave select coming from flash reader
- name: fr_din
port: fr_din
width: 4
direction: output
description: spi master data in going to the flash reader
- name: fr_dout
port: fr_dout
width: 4
direction: input
description: spi master data out coming from flash reader
- name: fr_douten
port: fr_douten
width: 4
direction: input
description: spi master data out enable coming from flash reader
- name: fm_sck
port: fm_sck
width: 1
direction: output
description: spi clock going to flash (slave)
- name: fm_ce_n
port: fm_ce_n
width: 1
direction: output
description: spi slave select going to flash (slave)
- name: fm_din
port: fm_din
width: 4
direction: input
description: spi master data in coming from flash (slave)
- name: fm_dout
port: fm_dout
width: 4
direction: output
description: spi master data out going to flash (slave)
- name: fm_douten
port: fm_douten
width: 4
direction: output
description: spi master data out enable going to flash (slave)
registers:
- name: WE
size: 1
mode: w
fifo: no
offset: 0
bit_access: no
write_port: ""
description: Write Enable; enables flash writer to write to flash
- name: SS
size: 1
mode: w
fifo: no
offset: 4
bit_access: no
write_port: ""
description: Slave Select; flash SS signal value
- name: SCK
size: 1
mode: w
fifo: no
offset: 8
bit_access: no
write_port: ""
description: Slave Clock; flash SCK signal value
- name: OE
size: 4
mode: w
fifo: no
offset: 12
bit_access: no
write_port: ""
description: Output enable for the four flash IOs
- name: DATAO
size: 4
mode: w
fifo: no
offset: 16
bit_access: no
write_port: ""
description: Output Data from the flash writer or controller going to flash
- name: DATAI
size: 4
mode: r
fifo: no
offset: 20
bit_access: no
write_port: ""
description: Input Data coming from flash flash
clock:
name: HCLK
reset:
name: HRESETn
level: 0
120 changes: 110 additions & 10 deletions README.md
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# AHB FLASH WRITER
## I/O Registers
| Register | Offset | Mode | Size | Description |
| -------- | ------ | ------------ | ------|----- |
| Write Enable | 0x0000 | RW | 1| Enables flash writer to write to flash |
| Slave Select | 0x0004 | RW | 1| Flash SS signal value |
| Slave Clock | 0x0008 | RW | 1| Flash SCK signal value |
| Output Enable | 0x000C | RW | 4| Output enable for the four flash IOs |
| Slave OUT | 0x0010 | RW | 4| output data from flash |
| Slave IN | 0x00014 | RW | 4| input data to flash |
# EF_QSPI_FLASH_WRITER

A Quad SPI Flash Writer used to program flash. It can be used along with flash controller to program the flash then read from it.
## The wrapped IP


The IP comes with an AHBL Wrapper

### Wrapped IP System Integration

```verilog
EF_QSPI_FLASH_WRITER INST (
`TB_AHBL_SLAVE_CONN,
.fr_sck(fr_sck),
.fr_ce_n(fr_ce_n),
.fr_din(fr_din),
.fr_dout(fr_dout),
.fr_douten(fr_douten),
.fm_sck(fm_sck),
.fm_ce_n(fm_ce_n),
.fm_din(fm_din),
.fm_dout(fm_dout),
.fm_douten(fm_douten)
);
```
> **_NOTE:_** `TB_AHBL_SLAVE_CONN is a convenient macro provided by [BusWrap](https://github.com/efabless/BusWrap/tree/main).
## Implementation example

The following table is the result for implementing the EF_QSPI_FLASH_WRITER IP with different wrappers using Sky130 PDK and [OpenLane2](https://github.com/efabless/openlane2) flow.
|Module | Number of cells | Max. freq |
|---|---|---|
|EF_QSPI_FLASH_WRITER|TBD|TBD|
## The Programmer's Interface


### Registers

|Name|Offset|Reset Value|Access Mode|Description|
|---|---|---|---|---|
|WE|0000|0x00000000|w|Write Enable; enables flash writer to write to flash|
|SS|0004|0x00000000|w|Slave Select; flash SS signal value|
|SCK|0008|0x00000000|w|Slave Clock; flash SCK signal value|
|OE|000c|0x00000000|w|Output enable for the four flash IOs|
|DATAO|0010|0x00000000|w|Output Data from the flash writer or controller going to flash|
|DATAI|0014|0x00000000|r|Input Data coming from flash flash|

### WE Register [Offset: 0x0, mode: w]

Write Enable; enables flash writer to write to flash
<img src="https://svg.wavedrom.com/{reg:[{name:'WE', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>


### SS Register [Offset: 0x4, mode: w]

Slave Select; flash SS signal value
<img src="https://svg.wavedrom.com/{reg:[{name:'SS', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>


### SCK Register [Offset: 0x8, mode: w]

Slave Clock; flash SCK signal value
<img src="https://svg.wavedrom.com/{reg:[{name:'SCK', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>


### OE Register [Offset: 0xc, mode: w]

Output enable for the four flash IOs
<img src="https://svg.wavedrom.com/{reg:[{name:'OE', bits:4},{bits: 28}], config: {lanes: 2, hflip: true}} "/>


### DATAO Register [Offset: 0x10, mode: w]

Output Data from the flash writer or controller going to flash
<img src="https://svg.wavedrom.com/{reg:[{name:'DATAO', bits:4},{bits: 28}], config: {lanes: 2, hflip: true}} "/>


### DATAI Register [Offset: 0x14, mode: r]

Input Data coming from flash flash
<img src="https://svg.wavedrom.com/{reg:[{name:'DATAI', bits:4},{bits: 28}], config: {lanes: 2, hflip: true}} "/>


### The Interface
<img src="docs/EF_QSPI_FLASH_WRITER.svg" width="600"/>

#### Ports

|Port|Direction|Width|Description|
|---|---|---|---|
|fr_sck|input|1|spi clock coming from flash reader|
|fr_ce_n|input|1|spi slave select coming from flash reader|
|fr_din|output|4|spi master data in going to the flash reader|
|fr_dout|input|4|spi master data out coming from flash reader|
|fr_douten|input|4|spi master data out enable coming from flash reader|
|fm_sck|output|1|spi clock going to flash (slave)|
|fm_ce_n|output|1|spi slave select going to flash (slave)|
|fm_din|input|4|spi master data in coming from flash (slave)|
|fm_dout|output|4|spi master data out going to flash (slave)|
|fm_douten|output|4|spi master data out enable going to flash (slave)|
## F/W Usage Guidelines:
TBD
## Installation:
You can either clone repo or use [IPM](https://github.com/efabless/IPM) which is an open-source IPs Package Manager
* To clone repo:
```git clone https://github.com/efabless/EF_QSPI_FLASH_WRITER```
* To download via IPM , follow installation guides [here](https://github.com/efabless/IPM/blob/main/README.md) then run
```ipm install EF_QSPI_FLASH_WRITER```
### Run cocotb UVM Testbench:
TBD
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