update wrappers and docs with the latest buswrap updates

EF_QSPI_XIP_CTRL.yaml

@@ -20,11 +20,13 @@ info:
   type": soft
   status: verified
   cell_count:
+    - IP: 1973
     - AHBL: 1973
   width": "0.0"
   height": "0.0"
   technology: n/a
   clock_freq_mhz:
+    - IP: 250
     - AHBL: 250
   digital_supply_voltage: n/a
   analog_supply_voltage: n/a
@@ -40,6 +42,10 @@ parameters:
     default: 999
     description: The number of cycles needed for the s/w reset command; reset time = (RESET_CYCLES + 1) * 2 /(HCLK frequency). 
 
+clock:
+  name: clk
+  gated: 'no'
+
 external_interface:
   - name: sck
     direction: output

README.md

@@ -1,99 +1,79 @@
 # EF_QSPI_XIP_CTRL
-Quad I/O SPI Flash memory controller with support for:
-- AHB lite interface
-- Execute in Place (XiP)
-- Nx16 Direct-Mapped Cache (default: N=32).
 
-Intended to be used with SoCs that have no on-chip flash memory. 
-
-
-## Performance
-The following data is obtained using Sky130 HD library
-| Configuration | # of Cells (K) | Delay (ns) | I<sub>dyn</sub> (mA/MHz) | I<sub>s</sub> (nA) | 
-|---------------|----------------|------------|--------------------------|--------------------|
-| 16x16 | 7.2 | 12 | 0.0625 | 20 |
-| 32x16 | 14.3 | 17  | 0.126 | 39.5 |
-
-
-AHB-Lite Quad I/O SPI Flash memory controller with direct mapped cache and support for XiP.
+A QSPI XiP Flash COntroller with a parameterized Direct-Mapped Cache.
 ## The wrapped IP
 
 
  The IP comes with an AHBL Wrapper
 
-### Wrapped IP System Integration
+#### Wrapped IP System Integration
 
 ```verilog
 EF_QSPI_XIP_CTRL_APB INST (
-        `TB_AHBL_SLAVE_CONN,
-        .sck(sck),
-        .ce_n(ce_n),
-        .din(din),
-        .dout(dout),
-        .douten(douten)
+	`TB_AHBL_SLAVE_CONN,
+	.sck(sck)
+	.ce_n(ce_n)
+	.dout(dout)
+	.din(din)
+	.douten(douten)
 );
 ```
 > **_NOTE:_** `TB_APB_SLAVE_CONN is a convenient macro provided by [BusWrap](https://github.com/efabless/BusWrap/tree/main).
+#### Wrappers with DFT support
+Wrappers in the directory ``/hdl/rtl/bus_wrappers/DFT`` have an extra input port ``sc_testmode`` to enable the clock gate whenever the scan chain testmode is enabled.
 
 ## Implementation example  
 
 The following table is the result for implementing the EF_QSPI_XIP_CTRL IP with different wrappers using Sky130 PDK and [OpenLane2](https://github.com/efabless/openlane2) flow.
 |Module | Number of cells | Max. freq |
 |---|---|---|
-|EF_QSPI_XIP_CTRL|534| 384 MHz |
-|EF_QSPI_XIP_CTRL_AHBL|13024|40 MHz|
+|EF_QSPI_XIP_CTRL|1973| 250 |
+|EF_QSPI_XIP_CTRL_AHBL|1973|250|
+## The Programmer's Interface
+
+
+### Registers
+
+|Name|Offset|Reset Value|Access Mode|Description|
+|---|---|---|---|---|
+
+### Clock Gating
+The IP has clock gating feature, enabling the selective activation and deactivation of the clock as required through the ``GCLK`` register. This functionality is implemented through the ``ef_util_gating_cell``, which is part of the the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the cell operates with a behavioral implementation, but when the ``CLKG_SKY130_HD`` macro is enabled, the ``sky130_fd_sc_hd__dlclkp_4`` clock gating cell is used.
+**Note:** If you choose the [OpenLane2](https://github.com/efabless/openlane2) flow for implementation and would like to add the clock gating feature, you need to add ``SKY130`` macro to the ``VERILOG_DEFINES`` configuration variable. Update the YAML configuration file as follows: 
+```
+VERILOG_DEFINES:
+- SKY130
+```
 
 ### The Interface 
-<img src="docs/EF_QSPI_XIP_CTRL.svg" width="600"/>
+
+<img src="docs/_static/EF_QSPI_XIP_CTRL.svg" width="600"/>
+
+#### Module Parameters 
+
+|Parameter|Description|Default Value|
+|---|---|---|
+|NUM_LINES|The cache number of lines.|16|
+|LINE_SIZE|The cache line size in bytes.|32|
+|RESET_CYCLES|The number of cycles needed for the s/w reset command; reset time = (RESET_CYCLES + 1) * 2 /(HCLK frequency).|999|
 
 #### Ports 
 
 |Port|Direction|Width|Description|
 |---|---|---|---|
-|sck|output|1|spi serial clock|
-|ce_n|output|1|slave select signal|
-|din|input|4|spi data in|
-|dout|output|4|spi data out|
-|douten|output|4|spi data out enable|
-
+|sck|output|1|SPI serial clock|
+|ce_n|output|1|SPI chip select (Active Low).|
+|dout|output|4|Flash controller SPI data out.|
+|din|input|4|Flash controller SPI data in.|
+|douten|output|4|Flash controller data out enable (Active Low)|
+## Firmware Drivers:
+Firmware drivers for EF_QSPI_XIP_CTRL can be found in the [fw](https://github.com/efabless/EF_QSPI_XIP_CTRL/tree/main/fw) directory. EF_QSPI_XIP_CTRL driver documentation  is available [here](https://github.com/efabless/EF_QSPI_XIP_CTRL/blob/main/fw/README.md).
+You can also find an example C application using the EF_QSPI_XIP_CTRL drivers [here]().
 ## Installation:
 You can either clone repo or use [IPM](https://github.com/efabless/IPM) which is an open-source IPs Package Manager
 * To clone repo:
-```git clone https://https://github.com/shalan/EF_QSPI_FLASH_CTRL```
+```git clone https://github.com/efabless/EF_QSPI_XIP_CTRL```
+> **Note:** If you choose this method, you need to clone [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) repository, as it includes required modules from the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v)
 * To download via IPM , follow installation guides [here](https://github.com/efabless/IPM/blob/main/README.md) then run 
 ```ipm install EF_QSPI_XIP_CTRL```
-### Run cocotb UVM Testbench:
-In IP directory run:
- ```shell
- cd verify/uvm-python/
- ```
- ##### To run testbench for design with APB 
- To run all tests:
- ```shell
- make run_all_tests BUS_TYPE=APB
- ```
- To run a certain test:
- ```shell
- make run_<test_name> BUS_TYPE=APB
- ```
- To run all tests with a tag: 
- ```shell
- make run_all_tests TAG=<new_tag> BUS_TYPE=APB
- ```
- ##### To run testbench for design with APB
- To run all tests:
- ```shell
- make run_all_tests BUS_TYPE=AHB
- ```
- To run a certain test:
- ```shell
- make run_<test_name> BUS_TYPE=AHB
- ```
- To run all tests with a tag: 
- ```shell
- make run_all_tests TAG=<new_tag> BUS_TYPE=AHB
-```
-
-## Todo:
- - [ ] support for WB bus
- - [ ] Support cache configurations other than 16 bytes per line
+> **Note:** This method is recommended as it automatically installs [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) as a dependency.