fix Testbench

efabless · Sep 30, 2024 · af562c7 · af562c7
1 parent 3f9f6b9
commit af562c7
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Showing 12 changed files with 360 additions and 73 deletions.
diff --git a/hdl/rtl/bus_wrappers/EF_TMR32_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_TMR32_AHBL.pp.v
@@ -21,12 +21,92 @@
 
 `timescale			1ns/1ps
 `default_nettype	none
+
+
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+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan ([email protected])
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
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 module EF_TMR32_AHBL #( 
 	parameter	
 		PRW = 16
 ) (
+
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 	input wire          HCLK,
                                         input wire          HRESETn,
                                         input wire          HWRITE,
@@ -39,9 +119,9 @@ module EF_TMR32_AHBL #(
                                         output wire [31:0]  HRDATA,
                                         output wire         IRQ
 ,
-	output	wire [1-1:0]	pwm0,
-	output	wire [1-1:0]	pwm1,
-	input	wire [1-1:0]	pwm_fault
+	output	wire	[1-1:0]	pwm0,
+	output	wire	[1-1:0]	pwm1,
+	input	wire	[1-1:0]	pwm_fault
 );
 
 	localparam	TMR_REG_OFFSET = 16'h0000;
@@ -59,7 +139,21 @@ module EF_TMR32_AHBL #(
 	localparam	MIS_REG_OFFSET = 16'hFF04;
 	localparam	RIS_REG_OFFSET = 16'hFF08;
 	localparam	IC_REG_OFFSET = 16'hFF0C;
-	wire		clk = HCLK;
+
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+
+
+
+ // USE_POWER_PINS
+        .clk(HCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+
+	wire		clk = clk_g;
 	wire		rst_n = HRESETn;
 
 
@@ -100,7 +194,7 @@ module EF_TMR32_AHBL #(
 	wire [32-1:0]	tmr;
 	wire [1-1:0]	matchx_flag;
 	wire [1-1:0]	matchy_flag;
-	(* keep *) wire [1-1:0]	timeout_flag;
+	wire [1-1:0]	timeout_flag;
 
 	// Register Definitions
 	wire [32-1:0]	TMR_WIRE;
@@ -172,6 +266,11 @@ module EF_TMR32_AHBL #(
                                         else if(ahbl_we & (last_HADDR[16-1:0]==PWMFC_REG_OFFSET))
                                             PWMFC_REG <= HWDATA[16-1:0];
 
+	localparam	GCLK_REG_OFFSET = 16'hFF10;
+	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) GCLK_REG <= 0;
+                                        else if(ahbl_we & (last_HADDR[16-1:0]==GCLK_REG_OFFSET))
+                                            GCLK_REG <= HWDATA[1-1:0];
+
 	reg [2:0] IM_REG;
 	reg [2:0] IC_REG;
 	reg [2:0] RIS_REG;
@@ -251,6 +350,7 @@ module EF_TMR32_AHBL #(
 			(last_HADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(last_HADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(last_HADDR[16-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(last_HADDR[16-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
 	assign	HREADYOUT = 1'b1;

diff --git a/hdl/rtl/bus_wrappers/EF_TMR32_AHBL.v b/hdl/rtl/bus_wrappers/EF_TMR32_AHBL.v
@@ -30,10 +30,14 @@ module EF_TMR32_AHBL #(
 	parameter	
 		PRW = 16
 ) (
+`ifdef USE_POWER_PINS
+	inout VPWR,
+	inout VGND,
+`endif
 	`AHBL_SLAVE_PORTS,
-	output	wire [1-1:0]	pwm0,
-	output	wire [1-1:0]	pwm1,
-	input	wire [1-1:0]	pwm_fault
+	output	wire	[1-1:0]	pwm0,
+	output	wire	[1-1:0]	pwm1,
+	input	wire	[1-1:0]	pwm_fault
 );
 
 	localparam	TMR_REG_OFFSET = `AHBL_AW'h0000;
@@ -51,7 +55,21 @@ module EF_TMR32_AHBL #(
 	localparam	MIS_REG_OFFSET = `AHBL_AW'hFF04;
 	localparam	RIS_REG_OFFSET = `AHBL_AW'hFF08;
 	localparam	IC_REG_OFFSET = `AHBL_AW'hFF0C;
-	wire		clk = HCLK;
+
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(HCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+
+	wire		clk = clk_g;
 	wire		rst_n = HRESETn;
 
 
@@ -128,6 +146,9 @@ module EF_TMR32_AHBL #(
 	assign	pwm_fault_clr = PWMFC_REG;
 	`AHBL_REG(PWMFC_REG, 0, 16)
 
+	localparam	GCLK_REG_OFFSET = `AHBL_AW'hFF10;
+	`AHBL_REG(GCLK_REG, 0, 1)
+
 	reg [2:0] IM_REG;
 	reg [2:0] IC_REG;
 	reg [2:0] RIS_REG;
@@ -202,6 +223,7 @@ module EF_TMR32_AHBL #(
 			(last_HADDR[`AHBL_AW-1:0] == MIS_REG_OFFSET)	? MIS_REG :
 			(last_HADDR[`AHBL_AW-1:0] == RIS_REG_OFFSET)	? RIS_REG :
 			(last_HADDR[`AHBL_AW-1:0] == IC_REG_OFFSET)	? IC_REG :
+			(last_HADDR[`AHBL_AW-1:0] == GCLK_REG_OFFSET)	? GCLK_REG :
 			32'hDEADBEEF;
 
 	assign	HREADYOUT = 1'b1;

diff --git a/hdl/rtl/bus_wrappers/EF_TMR32_APB.pp.v b/hdl/rtl/bus_wrappers/EF_TMR32_APB.pp.v
@@ -21,16 +21,90 @@
 
 `timescale			1ns/1ps
 `default_nettype	none
+
+
+
+/*
+	Copyright 2020 AUCOHL
+
+    Author: Mohamed Shalan ([email protected])
+	
+	Licensed under the Apache License, Version 2.0 (the "License"); 
+	you may not use this file except in compliance with the License. 
+	You may obtain a copy of the License at:
+
+	http://www.apache.org/licenses/LICENSE-2.0
+
+	Unless required by applicable law or agreed to in writing, software 
+	distributed under the License is distributed on an "AS IS" BASIS, 
+	WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 
+	See the License for the specific language governing permissions and 
+	limitations under the License.
+*/
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+
 
 
 module EF_TMR32_APB #( 
 	parameter	
 		PRW = 16
 ) (
-`ifdef USE_POWER_PINS
-	inout VPWR,
-	inout VGND,
-`endif
+
+
+
+
 	input wire          PCLK,
                                         input wire          PRESETn,
                                         input wire          PWRITE,
@@ -63,27 +137,20 @@ module EF_TMR32_APB #(
 	localparam	RIS_REG_OFFSET = 16'hFF08;
 	localparam	IC_REG_OFFSET = 16'hFF0C;
 
-        reg [0:0] GCLK_REG;
-        wire clk_g;
-        wire clk_gated_en = GCLK_REG[0];
-
-	`ifdef FPGA
-		wire clk = PCLK;
-	`else
-		(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
-		`ifdef USE_POWER_PINS 
-			.VPWR(VPWR), 
-			.VGND(VGND), 
-			.VNB(VGND),
-			.VPB(VPWR),
-		`endif
-			.GCLK(clk_g), 
-			.GATE(clk_gated_en), 
-			.CLK(PCLK)
-			);
-
-		wire		clk = clk_g;
-	`endif
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+
+
+
+ // USE_POWER_PINS
+        .clk(PCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+
+	wire		clk = clk_g;
 	wire		rst_n = PRESETn;
 
 

diff --git a/hdl/rtl/bus_wrappers/EF_TMR32_APB.v b/hdl/rtl/bus_wrappers/EF_TMR32_APB.v
@@ -56,27 +56,20 @@ module EF_TMR32_APB #(
 	localparam	RIS_REG_OFFSET = `APB_AW'hFF08;
 	localparam	IC_REG_OFFSET = `APB_AW'hFF0C;
 
-        reg [0:0] GCLK_REG;
-        wire clk_g;
-        wire clk_gated_en = GCLK_REG[0];
-
-	`ifdef FPGA
-		wire clk = PCLK;
-	`else
-		(* keep *) sky130_fd_sc_hd__dlclkp_4 clk_gate(
-		`ifdef USE_POWER_PINS 
-			.VPWR(VPWR), 
-			.VGND(VGND), 
-			.VNB(VGND),
-			.VPB(VPWR),
-		`endif
-			.GCLK(clk_g), 
-			.GATE(clk_gated_en), 
-			.CLK(PCLK)
-			);
-
-		wire		clk = clk_g;
-	`endif
+    reg [0:0] GCLK_REG;
+    wire clk_g;
+    wire clk_gated_en = GCLK_REG[0];
+    ef_gating_cell clk_gate_cell(
+        `ifdef USE_POWER_PINS 
+        .vpwr(VPWR),
+        .vgnd(VGND),
+        `endif // USE_POWER_PINS
+        .clk(PCLK),
+        .clk_en(clk_gated_en),
+        .clk_o(clk_g)
+    );
+
+	wire		clk = clk_g;
 	wire		rst_n = PRESETn;