regenerate wrappers and docs

EF_TMR32.yaml

@@ -21,8 +21,8 @@ A 32-bit timer and PWM generator with the following features:
   repo: github.com/efabless/EF_TMR32/tree/main
   owner: Efabless Corp.
   license: APACHE 2.0
-  author: Mohamed Shalan
-  email: mshalan@efabless.com
+  author: Efabless Corp.
+  email: ip_admin@efabless.com
   version: v1.0.11
   date: 8-10-2024
   category: digital
@@ -55,20 +55,6 @@ A 32-bit timer and PWM generator with the following features:
   analog_supply_voltage: n/a
   irq_reg_offset: 0xFF00
   fifo_reg_offset: 0xFE00
-  firmware_guidelines: |
-    * To use the timer only:
-    1. Set the value of reload (the maximum value the timer counter will reach if up counting or the value it will start from when down counting) by writing to ``RELOAD`` register
-    2. Set the timer counting frequency by writing to the ``PR`` register where  the timer counting frequency is $Clock\ freq/(PR + 1)$|
-    4. Choose whether you want the timer counter to be up counting, down counting, up/down counting by setting the ``DIR`` field in ``CFG`` register
-    5. Choose whether you want the timer counter to be periodic (starts counting again after reaching reload value) or one shot (count only one time and stays at reload value) by setting the ``P`` field in ``CFG`` register
-    6. Enable the timer by setting ``TE`` field in ``CTRL`` register , if one shot mode is used, use ``TS`` field to restart the counter
-    7. Get the actual timer value through reading ``TMR`` register
-        
-    * To generate pwm signals:
-    1. Do the exact same steps (from 1 to 5)  for using the timer 
-    2. Set the values for the two compare registers, if needed, by writing to ``CMPX`` and ``CMPY`` registers
-    3. Choose the actions you want when the timer reaches each of zero, cmpx (up counting), cmpy (up counting), reload, cmpx (down counting), cmpy (down counting). The actions could be either no action, high, low, or invert. You can set the actions by writing to ``PWM0CFG`` if using pwm0 or ``PWM1CFG`` if using pwm1.
-    4. Enable the timer, and enable pwm0 and/or pwm1 by writing to ``CTRL`` register
 
 
 parameters:
@@ -160,7 +146,7 @@ ports:
 
 
 clock:
- name: clk'
+ name: clk
  gated: "yes"
 
 reset:

README.md

@@ -12,22 +12,31 @@
 ## The wrapped IP
 
 
- APB, AHBL, and Wishbone wrappers, generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility, are provided. All wrappers provide the same programmer's interface as outlined in the following sections.
+ APB, AHBL, and Wishbone wrappers are provided. All wrappers provide the same programmer's interface as outlined in the following sections.
 
 #### Wrapped IP System Integration
 
-Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the APB wrapper:
+Based on your use case, use one of the provided wrappers or create a wrapper for your system bus type. For an example of how to integrate the wishbone wrapper:
 ```verilog
-EF_TMR32_APB INST (
-	`TB_APB_SLAVE_CONN,
+EF_TMR32_WB INST (
+	.clk_i(clk_i),
+	.rst_i(rst_i),
+	.adr_i(adr_i),
+	.dat_i(dat_i),
+	.dat_o(dat_o),
+	.sel_i(sel_i),
+	.cyc_i(cyc_i),
+	.stb_i(stb_i),
+	.ack_o(ack_o),
+	.we_i(we_i), 
+	.IRQ(irq),
 	.pwm0(pwm0),
 	.pwm1(pwm1),
 	.pwm_fault(pwm_fault)
 );
 ```
-> **_NOTE:_** `TB_APB_SLAVE_CONN is a convenient macro provided by [BusWrap](https://github.com/efabless/BusWrap/tree/main).
 #### Wrappers with DFT support
-Wrappers in the directory ``/hdl/rtl/bus_wrappers/DFT`` have an extra input port ``sc_testmode`` to enable the clock gate whenever the scan chain testmode is enabled.
+Wrappers in the directory ``/hdl/rtl/bus_wrappers/DFT`` have an extra input port ``sc_testmode`` to disable the clock gate whenever the scan chain testmode is enabled.
 
 ## Implementation example  
 
@@ -162,7 +171,7 @@ PWM fault clear register.
 
 ### Interrupt Flags
 
-The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility. 
+The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types.
 
 Each register has a group of bits for the interrupt sources/flags.
 - `IM` [offset: 0xff00]: is used to enable/disable interrupt sources.
@@ -182,7 +191,13 @@ The following are the bit definitions for the interrupt registers:
 |1|MX|1|TMR matches CMPX register.|
 |2|MY|1|TMR matches CMPY register.|
 ### Clock Gating
-The IP has clock gating feature, enabling the selective activation and deactivation of the clock as required through the ``GCLK`` register. This functionality is implemented through the ``ef_gating_cell``, which is part of the the common modules library, [aucohl_lib.v](https://github.com/efabless/IP_Utilities/blob/main/rtl/aucohl_lib.v). By default, the cell operates with a behavioral implementation, but when the ``SKY130`` macro is enabled, the ``sky130_fd_sc_hd__dlclkp_4`` clock gating cell is used.
+The IP has clock gating feature, enabling the selective activation and deactivation of the clock as required through the ``GCLK`` register. This functionality is implemented through the ``ef_util_gating_cell``, which is part of the the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v). By default, the cell operates with a behavioral implementation, but when the ``CLKG_SKY130_HD`` macro is enabled, the ``sky130_fd_sc_hd__dlclkp_4`` clock gating cell is used.
+
+**Note:** If you choose the [OpenLane2](https://github.com/efabless/openlane2) flow for implementation and would like to add the clock gating feature, you need to add ``CLKG_SKY130_HD`` macro to the ``VERILOG_DEFINES`` configuration variable. Update the YAML configuration file as follows: 
+```
+VERILOG_DEFINES:
+- CLKG_SKY130_HD
+```
 
 ### The Interface 
 
@@ -221,57 +236,14 @@ The IP has clock gating feature, enabling the selective activation and deactivat
 |matchx_flag|output|1|Flag raised when matching compare value x|
 |matchy_flag|output|1|Flag raised when matching compare value x|
 |timeout_flag|output|1|Flag raised when timeout happen|
-## F/W Usage Guidelines:
-* To use the timer only:
-1. Set the value of reload (the maximum value the timer counter will reach if up counting or the value it will start from when down counting) by writing to ``RELOAD`` register
-2. Set the timer counting frequency by writing to the ``PR`` register where  the timer counting frequency is $Clock\ freq/(PR + 1)$|
-4. Choose whether you want the timer counter to be up counting, down counting, up/down counting by setting the ``DIR`` field in ``CFG`` register
-5. Choose whether you want the timer counter to be periodic (starts counting again after reaching reload value) or one shot (count only one time and stays at reload value) by setting the ``P`` field in ``CFG`` register
-6. Enable the timer by setting ``TE`` field in ``CTRL`` register , if one shot mode is used, use ``TS`` field to restart the counter
-7. Get the actual timer value through reading ``TMR`` register
-
-* To generate pwm signals:
-1. Do the exact same steps (from 1 to 5)  for using the timer 
-2. Set the values for the two compare registers, if needed, by writing to ``CMPX`` and ``CMPY`` registers
-3. Choose the actions you want when the timer reaches each of zero, cmpx (up counting), cmpy (up counting), reload, cmpx (down counting), cmpy (down counting). The actions could be either no action, high, low, or invert. You can set the actions by writing to ``PWM0CFG`` if using pwm0 or ``PWM1CFG`` if using pwm1.
-4. Enable the timer, and enable pwm0 and/or pwm1 by writing to ``CTRL`` register
-
+## Firmware Drivers:
+Firmware drivers for EF_TMR32 can be found in the [fw](https://github.com/efabless/EF_TMR32/tree/main/fw) directory. EF_TMR32 driver documentation  is available [here](https://github.com/efabless/EF_TMR32/blob/main/fw/README.md).
+You can also find an example C application using the EF_TMR32 drivers [here]().
 ## Installation:
 You can either clone repo or use [IPM](https://github.com/efabless/IPM) which is an open-source IPs Package Manager
 * To clone repo:
 ```git clone https://github.com/efabless/EF_TMR32/tree/main```
-> **Note:** If you choose this method, you need to clone [IP_Utilities](https://github.com/efabless/IP_Utilities/tree/main) repository, as it includes required modules from the common modules library, [aucohl_lib.v](https://github.com/efabless/IP_Utilities/blob/main/rtl/aucohl_lib.v)
+> **Note:** If you choose this method, you need to clone [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) repository, as it includes required modules from the common modules library, [ef_util_lib.v](https://github.com/efabless/EF_IP_UTIL/blob/main/hdl/ef_util_lib.v)
 * To download via IPM , follow installation guides [here](https://github.com/efabless/IPM/blob/main/README.md) then run 
 ```ipm install EF_TMR32```
-> **Note:** This method is recommended as it automatically installs [IP_Utilities](https://github.com/efabless/IP_Utilities/tree/main) as a dependency.
-### Run cocotb UVM Testbench:
-In IP directory run:
- ```shell
- cd verify/uvm-python/
- ```
- ##### To run testbench for design with APB 
- To run all tests:
- ```shell
- make run_all_tests BUS_TYPE=APB
- ```
- To run a certain test:
- ```shell
- make run_<test_name> BUS_TYPE=APB
- ```
- To run all tests with a tag: 
- ```shell
- make run_all_tests TAG=<new_tag> BUS_TYPE=APB
- ```
- ##### To run testbench for design with APB
- To run all tests:
- ```shell
- make run_all_tests BUS_TYPE=AHB
- ```
- To run a certain test:
- ```shell
- make run_<test_name> BUS_TYPE=AHB
- ```
- To run all tests with a tag: 
- ```shell
- make run_all_tests TAG=<new_tag> BUS_TYPE=AHB
-```
+> **Note:** This method is recommended as it automatically installs [EF_IP_UTIL](https://github.com/efabless/EF_IP_UTIL.git) as a dependency.