update documentation

README.md

@@ -42,7 +42,7 @@ EF_UART_APB INST (
 ```
 > **_NOTE:_** `TB_APB_SLAVE_CONN is a convenient macro provided by [BusWrap](https://github.com/efabless/BusWrap/tree/main).
 #### Wrappers with DFT support
-Wrappers in the directory ``/hdl/rtl/bus_wrappers/DFT`` have an extra input port to enable the clock gate whenever the scan chain testmode is enabled.
+Wrappers in the directory ``/hdl/rtl/bus_wrappers/DFT`` have an extra input port ``sc_testmode`` to enable the clock gate whenever the scan chain testmode is enabled.
 
 ## Implementation example  
 
@@ -83,19 +83,16 @@ The following table is the result for implementing the EF_UART IP with different
 RX Data register; the interface to the Receive FIFO.
 <img src="https://svg.wavedrom.com/{reg:[{name:'RXDATA', bits:9},{bits: 23}], config: {lanes: 2, hflip: true}} "/>
 
-
 ### TXDATA Register [Offset: 0x4, mode: w]
 
 TX Data register; ; the interface to the Receive FIFO.
 <img src="https://svg.wavedrom.com/{reg:[{name:'TXDATA', bits:9},{bits: 23}], config: {lanes: 2, hflip: true}} "/>
 
-
 ### PR Register [Offset: 0x8, mode: w]
 
 The Prescaler register; used to determine the baud rate. $baud_rate = clock_freq/((PR+1)*16)$.
 <img src="https://svg.wavedrom.com/{reg:[{name:'PR', bits:16},{bits: 16}], config: {lanes: 2, hflip: true}} "/>
 
-
 ### CTRL Register [Offset: 0xc, mode: w]
 
 UART Control Register
@@ -109,7 +106,6 @@ UART Control Register
 |3|lpen|1|Loopback (connect RX and TX pins together) enable|
 |4|gfen|1|UART Glitch Filer on RX enable|
 
-
 ### CFG Register [Offset: 0x10, mode: w]
 
 UART Configuration Register
@@ -122,13 +118,11 @@ UART Configuration Register
 |5|parity|3|Parity Type: 000: None, 001: odd, 010: even, 100: Sticky 0, 101: Sticky 1|
 |8|timeout|6|Receiver Timeout measured in number of bits|
 
-
 ### MATCH Register [Offset: 0x1c, mode: w]
 
 Match Register
 <img src="https://svg.wavedrom.com/{reg:[{name:'MATCH', bits:9},{bits: 23}], config: {lanes: 2, hflip: true}} "/>
 
-
 ### RX_FIFO_LEVEL Register [Offset: 0xfe00, mode: r]
 
 RX_FIFO Level Register
@@ -138,7 +132,6 @@ RX_FIFO Level Register
 |---|---|---|---|
 |0|level|4|FIFO data level|
 
-
 ### RX_FIFO_THRESHOLD Register [Offset: 0xfe04, mode: w]
 
 RX_FIFO Level Threshold Register
@@ -148,7 +141,6 @@ RX_FIFO Level Threshold Register
 |---|---|---|---|
 |0|threshold|4|FIFO level threshold value|
 
-
 ### RX_FIFO_FLUSH Register [Offset: 0xfe08, mode: w]
 
 RX_FIFO Flush Register
@@ -158,7 +150,6 @@ RX_FIFO Flush Register
 |---|---|---|---|
 |0|flush|1|FIFO flush|
 
-
 ### TX_FIFO_LEVEL Register [Offset: 0xfe10, mode: r]
 
 TX_FIFO Level Register
@@ -168,7 +159,6 @@ TX_FIFO Level Register
 |---|---|---|---|
 |0|level|4|FIFO data level|
 
-
 ### TX_FIFO_THRESHOLD Register [Offset: 0xfe14, mode: w]
 
 TX_FIFO Level Threshold Register
@@ -178,7 +168,6 @@ TX_FIFO Level Threshold Register
 |---|---|---|---|
 |0|threshold|4|FIFO level threshold value|
 
-
 ### TX_FIFO_FLUSH Register [Offset: 0xfe18, mode: w]
 
 TX_FIFO Flush Register
@@ -188,19 +177,28 @@ TX_FIFO Flush Register
 |---|---|---|---|
 |0|flush|1|FIFO flush|
 
+### GCLK Register [Offset: 0xff10, mode: w]
+
+ Gated clock enable register
+<img src="https://svg.wavedrom.com/{reg:[{name:'gclk_enable', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>
+
+|bit|field name|width|description|
+|---|---|---|---|
+|0|gclk_enable|1|Gated clock enable; 1: enable clock, 0: disable clock|
+
 
 ### Interrupt Flags
 
 The wrapped IP provides four registers to deal with interrupts: IM, RIS, MIS and IC. These registers exist for all wrapper types generated by the [BusWrap](https://github.com/efabless/BusWrap/tree/main) `bus_wrap.py` utility. 
 
 Each register has a group of bits for the interrupt sources/flags.
-- `IM`: is used to enable/disable interrupt sources.
+- `IM` [offset: 0xff00]: is used to enable/disable interrupt sources.
 
-- `RIS`: has the current interrupt status (interrupt flags) whether they are enabled or disabled.
+- `RIS` [offset: 0xff08]: has the current interrupt status (interrupt flags) whether they are enabled or disabled.
 
-- `MIS`: is the result of masking (ANDing) RIS by IM.
+- `MIS` [offset: 0xff04]: is the result of masking (ANDing) RIS by IM.
 
-- `IC`: is used to clear an interrupt flag.
+- `IC` [offset: 0xff0c]: is used to clear an interrupt flag.
 
 
 The following are the bit definitions for the interrupt registers: