changed fifos and irqs offset and regenerated wrappers and docs

efabless · May 8, 2024 · b9a9882 · b9a9882
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diff --git a/EF_UART.yaml b/EF_UART.yaml
@@ -7,8 +7,8 @@ info:
   license: APACHE 2.0
   author: Mohamed Shalan
   email: [email protected]
-  version: v1.1.0
-  date: 15-4-2024
+  version: v1.1.1
+  date: 07-5-2024
   category: digital
   tags:
     - peripheral
@@ -33,6 +33,8 @@ info:
     - WB: 83
   digital_supply_voltage: n/a
   analog_supply_voltage: n/a
+  irq_reg_offset: 0xFF00
+  fifo_reg_offset: 0xFE00
 
 parameters:
   - name: SC

diff --git a/README.md b/README.md
@@ -58,77 +58,62 @@ The following table is the result for implementing the EF_UART IP with different
 
 ### Registers
 
-
 |Name|Offset|Reset Value|Access Mode|Description|
 |---|---|---|---|---|
 |RXDATA|0000|0x00000000|r|RX Data register; the interface to the Receive FIFO.|
 |TXDATA|0004|0x00000000|w|TX Data register; ; the interface to the Receive FIFO.|
 |PR|0008|0x00000000|w|The Prescaler register; used to determine the baud rate. $baud_rate = clock_freq/((PR+1)*16)$.|
 |CTRL|000c|0x00000000|w|UART Control Register|
 |CFG|0010|0x00003F08|w|UART Configuration Register|
-|FIFOCTRL|0014|0x00000000|w|FIFO Control Register|
-|FIFOS|0018|0x00000000|r|FIFO Status Register|
 |MATCH|001c|0x00000000|w|Match Register|
-|IM|0f00|0x00000000|w|Interrupt Mask Register; write 1/0 to enable/disable interrupts; check the interrupt flags table for more details|
-|RIS|0f08|0x00000000|w|Raw Interrupt Status; reflects the current interrupts status;check the interrupt flags table for more details|
-|MIS|0f04|0x00000000|w|Masked Interrupt Status; On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect; check the interrupt flags table for more details|
-|IC|0f0c|0x00000000|w|Interrupt Clear Register; On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared; check the interrupt flags table for more details|
-
+|RX_FIFO_LEVEL|fe00|0x00000000|r|RX_FIFO Level Register|
+|RX_FIFO_THRESHOLD|fe04|0x00000000|w|RX_FIFO Level Threshold Register|
+|RX_FIFO_FLUSH|fe08|0x00000000|w|RX_FIFO Flush Register|
+|TX_FIFO_LEVEL|fe10|0x00000000|r|TX_FIFO Level Register|
+|TX_FIFO_THRESHOLD|fe14|0x00000000|w|TX_FIFO Level Threshold Register|
+|TX_FIFO_FLUSH|fe18|0x00000000|w|TX_FIFO Flush Register|
+|IM|ff00|0x00000000|w|Interrupt Mask Register; write 1/0 to enable/disable interrupts; check the interrupt flags table for more details|
+|RIS|ff08|0x00000000|w|Raw Interrupt Status; reflects the current interrupts status;check the interrupt flags table for more details|
+|MIS|ff04|0x00000000|w|Masked Interrupt Status; On a read, this register gives the current masked status value of the corresponding interrupt. A write has no effect; check the interrupt flags table for more details|
+|IC|ff0c|0x00000000|w|Interrupt Clear Register; On a write of 1, the corresponding interrupt (both raw interrupt and masked interrupt, if enabled) is cleared; check the interrupt flags table for more details|
 
 ### RXDATA Register [Offset: 0x0, mode: r]
 
-
 RX Data register; the interface to the Receive FIFO.
 <img src="https://svg.wavedrom.com/{reg:[{name:'RXDATA', bits:9},{bits: 23}], config: {lanes: 2, hflip: true}} "/>
 
 
-
-
 ### TXDATA Register [Offset: 0x4, mode: w]
 
-
 TX Data register; ; the interface to the Receive FIFO.
 <img src="https://svg.wavedrom.com/{reg:[{name:'TXDATA', bits:9},{bits: 23}], config: {lanes: 2, hflip: true}} "/>
 
 
-
-
 ### PR Register [Offset: 0x8, mode: w]
 
-
 The Prescaler register; used to determine the baud rate. $baud_rate = clock_freq/((PR+1)*16)$.
-
-
 <img src="https://svg.wavedrom.com/{reg:[{name:'PR', bits:16},{bits: 16}], config: {lanes: 2, hflip: true}} "/>
 
 
-
-
 ### CTRL Register [Offset: 0xc, mode: w]
 
-
 UART Control Register
 <img src="https://svg.wavedrom.com/{reg:[{name:'en', bits:1},{name:'txen', bits:1},{name:'rxen', bits:1},{name:'lpen', bits:1},{name:'gfen', bits:1},{bits: 27}], config: {lanes: 2, hflip: true}} "/>
 
-
 |bit|field name|width|description|
 |---|---|---|---|
 |0|en|1|UART enable|
 |1|txen|1|UART Transmitter enable|
 |2|rxen|1|UART Receiver enable|
 |3|lpen|1|Loopback (connect RX and TX pins together) enable|
-|4|gfen|1|UART Glitch Filter on RX enable|
-
-
+|4|gfen|1|UART Glitch Filer on RX enable|
 
 
 ### CFG Register [Offset: 0x10, mode: w]
 
-
 UART Configuration Register
 <img src="https://svg.wavedrom.com/{reg:[{name:'wlen', bits:4},{name:'stp2', bits:1},{name:'parity', bits:3},{name:'timeout', bits:6},{bits: 18}], config: {lanes: 2, hflip: true}} "/>
 
-
 |bit|field name|width|description|
 |---|---|---|---|
 |0|wlen|4|Data word length: 5-9 bits|
@@ -137,45 +122,70 @@ UART Configuration Register
 |8|timeout|6|Receiver Timeout measured in number of bits|
 
 
+### MATCH Register [Offset: 0x1c, mode: w]
+
+Match Register
+<img src="https://svg.wavedrom.com/{reg:[{name:'MATCH', bits:9},{bits: 23}], config: {lanes: 2, hflip: true}} "/>
 
 
-### FIFOCTRL Register [Offset: 0x14, mode: w]
+### RX_FIFO_LEVEL Register [Offset: 0xfe00, mode: r]
+
+RX_FIFO Level Register
+<img src="https://svg.wavedrom.com/{reg:[{name:'level', bits:4},{bits: 28}], config: {lanes: 2, hflip: true}} "/>
+
+|bit|field name|width|description|
+|---|---|---|---|
+|0|level|4|FIFO data level|
 
 
-FIFO Control Register
-<img src="https://svg.wavedrom.com/{reg:[{name:'TXLT', bits:4},{bits: 4},{name:'RXLT', bits:4},{bits: 20}], config: {lanes: 2, hflip: true}} "/>
+### RX_FIFO_THRESHOLD Register [Offset: 0xfe04, mode: w]
 
+RX_FIFO Level Threshold Register
+<img src="https://svg.wavedrom.com/{reg:[{name:'threshold', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>
 
 |bit|field name|width|description|
 |---|---|---|---|
-|0|TXLT|4|Transmit FIFO Level Threshold|
-|8|RXLT|4|Receive FIFO Level Threshold|
+|0|threshold|1|FIFO level threshold value|
 
 
+### RX_FIFO_FLUSH Register [Offset: 0xfe08, mode: w]
 
+RX_FIFO Flush Register
+<img src="https://svg.wavedrom.com/{reg:[{name:'flush', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>
 
-### FIFOS Register [Offset: 0x18, mode: r]
+|bit|field name|width|description|
+|---|---|---|---|
+|0|flush|1|FIFO flush|
 
 
-FIFO Status Register
-<img src="https://svg.wavedrom.com/{reg:[{name:'RXL', bits:4},{bits: 4},{name:'TXL', bits:4},{bits: 20}], config: {lanes: 2, hflip: true}} "/>
+### TX_FIFO_LEVEL Register [Offset: 0xfe10, mode: r]
 
+TX_FIFO Level Register
+<img src="https://svg.wavedrom.com/{reg:[{name:'level', bits:4},{bits: 28}], config: {lanes: 2, hflip: true}} "/>
 
 |bit|field name|width|description|
 |---|---|---|---|
-|0|RXL|4|Receive FIFO Level|
-|8|TXL|4|Transmit FIFO Level|
+|0|level|4|FIFO data level|
 
 
+### TX_FIFO_THRESHOLD Register [Offset: 0xfe14, mode: w]
 
+TX_FIFO Level Threshold Register
+<img src="https://svg.wavedrom.com/{reg:[{name:'threshold', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>
 
-### MATCH Register [Offset: 0x1c, mode: w]
+|bit|field name|width|description|
+|---|---|---|---|
+|0|threshold|1|FIFO level threshold value|
 
 
-Match Register
-<img src="https://svg.wavedrom.com/{reg:[{name:'MATCH', bits:9},{bits: 23}], config: {lanes: 2, hflip: true}} "/>
+### TX_FIFO_FLUSH Register [Offset: 0xfe18, mode: w]
 
+TX_FIFO Flush Register
+<img src="https://svg.wavedrom.com/{reg:[{name:'flush', bits:1},{bits: 31}], config: {lanes: 2, hflip: true}} "/>
 
+|bit|field name|width|description|
+|---|---|---|---|
+|0|flush|1|FIFO flush|
 
 
 ### Interrupt Flags

diff --git a/hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v b/hdl/rtl/bus_wrappers/EF_UART_AHBL.pp.v
@@ -122,23 +122,22 @@ module EF_UART_AHBL #(
 	output	[1-1:0]	tx
 );
 
-	localparam	RXDATA_REG_OFFSET = 16'd0;
-	localparam	TXDATA_REG_OFFSET = 16'd4;
-	localparam	PR_REG_OFFSET = 16'd8;
-	localparam	CTRL_REG_OFFSET = 16'd12;
-	localparam	CFG_REG_OFFSET = 16'd16;
-	localparam	MATCH_REG_OFFSET = 16'd28;
-	localparam	IM_REG_OFFSET = 16'd3840;
-	localparam	MIS_REG_OFFSET = 16'd3844;
-	localparam	RIS_REG_OFFSET = 16'd3848;
-	localparam	IC_REG_OFFSET = 16'd3852;
-	localparam	RX_FIFO_FLUSH_REG_OFFSET = 16'd4096;
-	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = 16'd4100;
-	localparam	RX_FIFO_LEVEL_REG_OFFSET = 16'd4104;
-	localparam	TX_FIFO_FLUSH_REG_OFFSET = 16'd4112;
-	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = 16'd4116;
-	localparam	TX_FIFO_LEVEL_REG_OFFSET = 16'd4120;
-
+	localparam	RXDATA_REG_OFFSET = 16'h0000;
+	localparam	TXDATA_REG_OFFSET = 16'h0004;
+	localparam	PR_REG_OFFSET = 16'h0008;
+	localparam	CTRL_REG_OFFSET = 16'h000C;
+	localparam	CFG_REG_OFFSET = 16'h0010;
+	localparam	MATCH_REG_OFFSET = 16'h001C;
+	localparam	RX_FIFO_LEVEL_REG_OFFSET = 16'hFE00;
+	localparam	RX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE04;
+	localparam	RX_FIFO_FLUSH_REG_OFFSET = 16'hFE08;
+	localparam	TX_FIFO_LEVEL_REG_OFFSET = 16'hFE10;
+	localparam	TX_FIFO_THRESHOLD_REG_OFFSET = 16'hFE14;
+	localparam	TX_FIFO_FLUSH_REG_OFFSET = 16'hFE18;
+	localparam	IM_REG_OFFSET = 16'hFF00;
+	localparam	MIS_REG_OFFSET = 16'hFF04;
+	localparam	RIS_REG_OFFSET = 16'hFF08;
+	localparam	IC_REG_OFFSET = 16'hFF0C;
 	wire		clk = HCLK;
 	wire		rst_n = HRESETn;
 
@@ -195,40 +194,6 @@ module EF_UART_AHBL #(
 	wire [1-1:0]	overrun_flag;
 	wire [1-1:0]	timeout_flag;
 
-	// FIFO Registers
-	// RX_FIFO Registers
-	reg	[FAW-1:0]	RX_FIFO_THRESHOLD_REG;
-	assign		rxfifotr = RX_FIFO_THRESHOLD_REG;
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
-                                            RX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];
-	wire	[FAW-1:0]	RX_FIFO_LEVEL_REG;
-	assign		RX_FIFO_LEVEL_REG = rx_level;
-	reg		RX_FIFO_FLUSH_REG;
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_FLUSH_REG <= 0;
-                                                else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_FLUSH_REG_OFFSET))
-                                                    RX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
-                                                else
-                                                    RX_FIFO_FLUSH_REG <= 'd0;
-	assign		rx_fifo_flush = RX_FIFO_FLUSH_REG;
-
-	// TX_FIFO Registers
-	reg	[FAW-1:0]	TX_FIFO_THRESHOLD_REG;
-	assign		txfifotr = TX_FIFO_THRESHOLD_REG;
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) TX_FIFO_THRESHOLD_REG <= 0;
-                                        else if(ahbl_we & (last_HADDR[16-1:0]==TX_FIFO_THRESHOLD_REG_OFFSET))
-                                            TX_FIFO_THRESHOLD_REG <= HWDATA[FAW-1:0];
-	wire	[FAW-1:0]	TX_FIFO_LEVEL_REG;
-	assign		TX_FIFO_LEVEL_REG = tx_level;
-	reg		TX_FIFO_FLUSH_REG;
-	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) TX_FIFO_FLUSH_REG <= 0;
-                                                else if(ahbl_we & (last_HADDR[16-1:0]==TX_FIFO_FLUSH_REG_OFFSET))
-                                                    TX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
-                                                else
-                                                    TX_FIFO_FLUSH_REG <= 'd0;
-	assign		tx_fifo_flush = TX_FIFO_FLUSH_REG;
-
-
 	// Register Definitions
 	wire	[MDW-1:0]	RXDATA_WIRE;
 
@@ -265,6 +230,40 @@ module EF_UART_AHBL #(
                                         else if(ahbl_we & (last_HADDR[16-1:0]==MATCH_REG_OFFSET))
                                             MATCH_REG <= HWDATA[MDW-1:0];
 
+	wire [FAW-1:0]	RX_FIFO_LEVEL_WIRE;
+	assign	RX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = rx_level;
+
+	reg [0:0]	RX_FIFO_THRESHOLD_REG;
+	assign	rxfifotr	=	RX_FIFO_THRESHOLD_REG[0 : 0];
+	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_THRESHOLD_REG <= 0;
+                                        else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_THRESHOLD_REG_OFFSET))
+                                            RX_FIFO_THRESHOLD_REG <= HWDATA[1-1:0];
+
+	reg [0:0]	RX_FIFO_FLUSH_REG;
+	assign	rx_fifo_flush	=	RX_FIFO_FLUSH_REG[0 : 0];
+	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) RX_FIFO_FLUSH_REG <= 0;
+                                                else if(ahbl_we & (last_HADDR[16-1:0]==RX_FIFO_FLUSH_REG_OFFSET))
+                                                    RX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
+                                                else
+                                                    RX_FIFO_FLUSH_REG <= 1'h0 & RX_FIFO_FLUSH_REG;
+
+	wire [FAW-1:0]	TX_FIFO_LEVEL_WIRE;
+	assign	TX_FIFO_LEVEL_WIRE[(FAW - 1) : 0] = tx_level;
+
+	reg [0:0]	TX_FIFO_THRESHOLD_REG;
+	assign	txfifotr	=	TX_FIFO_THRESHOLD_REG[0 : 0];
+	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) TX_FIFO_THRESHOLD_REG <= 0;
+                                        else if(ahbl_we & (last_HADDR[16-1:0]==TX_FIFO_THRESHOLD_REG_OFFSET))
+                                            TX_FIFO_THRESHOLD_REG <= HWDATA[1-1:0];
+
+	reg [0:0]	TX_FIFO_FLUSH_REG;
+	assign	tx_fifo_flush	=	TX_FIFO_FLUSH_REG[0 : 0];
+	always @(posedge HCLK or negedge HRESETn) if(~HRESETn) TX_FIFO_FLUSH_REG <= 0;
+                                                else if(ahbl_we & (last_HADDR[16-1:0]==TX_FIFO_FLUSH_REG_OFFSET))
+                                                    TX_FIFO_FLUSH_REG <= HWDATA[1-1:0];
+                                                else
+                                                    TX_FIFO_FLUSH_REG <= 1'h0 & TX_FIFO_FLUSH_REG;
+
 	reg [9:0] IM_REG;
 	reg [9:0] IC_REG;
 	reg [9:0] RIS_REG;
@@ -378,16 +377,16 @@ module EF_UART_AHBL #(
 			(last_HADDR[16-1:0] == CTRL_REG_OFFSET)	? CTRL_REG :
 			(last_HADDR[16-1:0] == CFG_REG_OFFSET)	? CFG_REG :
 			(last_HADDR[16-1:0] == MATCH_REG_OFFSET)	? MATCH_REG :
-			(last_HADDR[16-1:0] == IM_REG_OFFSET)	? IM_REG :
-			(last_HADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
-			(last_HADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
-			(last_HADDR[16-1:0] == IC_REG_OFFSET)	? IC_REG :
-			(last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_REG :
+			(last_HADDR[16-1:0] == RX_FIFO_LEVEL_REG_OFFSET)	? RX_FIFO_LEVEL_WIRE :
 			(last_HADDR[16-1:0] == RX_FIFO_THRESHOLD_REG_OFFSET)	? RX_FIFO_THRESHOLD_REG :
 			(last_HADDR[16-1:0] == RX_FIFO_FLUSH_REG_OFFSET)	? RX_FIFO_FLUSH_REG :
-			(last_HADDR[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_REG :
+			(last_HADDR[16-1:0] == TX_FIFO_LEVEL_REG_OFFSET)	? TX_FIFO_LEVEL_WIRE :
 			(last_HADDR[16-1:0] == TX_FIFO_THRESHOLD_REG_OFFSET)	? TX_FIFO_THRESHOLD_REG :
 			(last_HADDR[16-1:0] == TX_FIFO_FLUSH_REG_OFFSET)	? TX_FIFO_FLUSH_REG :
+			(last_HADDR[16-1:0] == IM_REG_OFFSET)	? IM_REG :
+			(last_HADDR[16-1:0] == MIS_REG_OFFSET)	? MIS_REG :
+			(last_HADDR[16-1:0] == RIS_REG_OFFSET)	? RIS_REG :
+			(last_HADDR[16-1:0] == IC_REG_OFFSET)	? IC_REG :
 			32'hDEADBEEF;
 
 	assign	HREADYOUT = 1'b1;