Merge pull request #27 from efabless/fix_piping_hready

Fix piping hready
efabless · Oct 10, 2024 · 60774ba · 60774ba
2 parents 9559317 + 3df1769
commit 60774ba
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Showing 2 changed files with 17 additions and 9 deletions.
diff --git a/.github/test_set.yaml b/.github/test_set.yaml
@@ -9,7 +9,7 @@
 - name: EF_UART
   url: https://github.com/efabless/EF_UART.git
   tests:
-    - TX_StressTest RX_StressTest LoopbackTest PrescalarStressTest 
+    - TX_StressTest LoopbackTest PrescalarStressTest 
     - LengthParityTXStressTest LengthParityRXStressTest WriteReadRegsTest
   bus:
     - APB
@@ -19,13 +19,13 @@
   url: https://github.com/efabless/EF_TMR32.git
   tests:
     - pwm_actions_test time_vary_test 
-    - pwm_pr_test pwm_tmr_test
+    - pwm_pr_test
   bus:
     - APB
     - AHB
     - WISHBONE
-- name: MS_QSPI_XIP_CACHE
-  url: https://github.com/efabless/MS_QSPI_XIP_CACHE.git
+- name: EF_QSPI_XIP_CTRL
+  url: https://github.com/efabless/EF_QSPI_XIP_CTRL.git
   tests:
     - flashReadTest flashResetTest flashRdWrTest
   bus:

diff --git a/bus_env/bus_agent/bus_ahb_driver.py b/bus_env/bus_agent/bus_ahb_driver.py
@@ -16,6 +16,7 @@ def __init__(self, name="bus_ahb_driver", parent=None):
 
     async def run_phase(self, phase):
         uvm_info(self.tag, "run_phase started", UVM_MEDIUM)
+        self.vif.HREADY.value = 0b01
         while True:
             tr = []
             await self.seq_item_port.get_next_item(tr)
@@ -41,8 +42,6 @@ async def run_phase(self, phase):
                 if not self.piping_q.empty():
                     tr = await self.piping_q.get_no_pop()
                     await self.address_phase(tr)
-                if self.piping_q.qsize() == 1:
-                    self.end_of_trans()
                 if not self.piping_q.empty():
                     await self.data_phase_lock.acquire()
                     tr = await self.piping_q.get()
@@ -63,7 +62,6 @@ async def address_phase(self, tr):
         self.vif.HADDR.value = tr.addr
         self.vif.HTRANS.value = 0b10
         self.vif.HSEL.value = 0b01
-        self.vif.HREADY.value = 0b01
         self.drv_optional_signals_address(tr)
         # TODO: HSIZE should be existed in the DUT wait until it got added
         await self.drive_delay()
@@ -90,9 +88,17 @@ async def data_phase(self, tr):
                 await self.drive_delay()
         else:
             # for reading just wait until the data is ready
+            if self.vif.HREADYOUT.value == 0:
+                self.vif.HREADY.value = 0b0
             await self.drive_delay()
-            while self.vif.HREADYOUT.value == 0:
+            while True:
+                await NextTimeStep()
+                if self.vif.HREADYOUT.value == 1:
+                    break
+                self.vif.HREADY.value = 0b0
                 await self.drive_delay()
+            uvm_info(self.tag, f"HREADYOUT is {self.vif.HREADYOUT.value}", UVM_MEDIUM)
+            self.vif.HREADY.value = 0b1
             try:
                 tr.data = self.vif.HRDATA.value.integer
             except ValueError:
@@ -107,10 +113,12 @@ async def data_phase(self, tr):
         )
         self.seq_item_port.put_response(tr)
         self.data_phase_lock.release()
+        if self.piping_q.empty():
+            self.end_of_trans()
 
     def end_of_trans(self):
         self.vif.HSEL.value = 0b00
-        self.vif.HREADY.value = 0b01
+        # self.vif.HREADY.value = 0b01
         self.vif.HTRANS.value = 0b00
         self.vif.HWRITE.value = 0