Added SOFA task and some benchmarks

VERSION.md

@@ -1 +1 @@
-1.2.971
+1.2.989

openfpga_flow/benchmarks/micro_benchmark/Decoder/Decoder_3_to_8/decoder_3_to_8.v

@@ -0,0 +1,28 @@
+module decoder_3_to_8( in, out, en);
+input [2:0]  in;
+input en;
+output [7:0] out;
+  reg [7:0] out;
+
+ always @( in or en)
+	begin
+
+      if (en) 
+        begin
+          out=8'd0;
+          case (in)
+              3'b000: out[0]=1'b1;
+              3'b001: out[1]=1'b1;
+              3'b010: out[2]=1'b1;
+              3'b011: out[3]=1'b1;
+              3'b100: out[4]=1'b1;
+              3'b101: out[5]=1'b1;
+              3'b110: out[6]=1'b1;
+              3'b111: out[7]=1'b1;
+              default: out=8'd0;
+          endcase
+      end
+else 
+out=8'd0;
+end
+endmodule

openfpga_flow/benchmarks/micro_benchmark/and2_9bits.v

@@ -0,0 +1,18 @@
+/////////////////////////////////////////
+//  Functionality: 2-input AND 
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module and2_9bits(
+  a,
+  b,
+  c);
+
+input wire [8:0] a;
+input wire [8:0] b;
+output wire [8:0] c;
+
+assign c = a & b;
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/and2_latch/and2_latch.v

@@ -10,10 +10,12 @@ module and2_latch(
   a,
   b,
   clk,
+  rst,
   c,
   d);
 
 input wire clk;
+input wire rst;
 
 input wire a;
 input wire b;
@@ -22,8 +24,11 @@ output reg d;
 
 assign c = a & b;
 
-always @(posedge clk) begin
-  d <= c;
+always @(posedge rst or posedge clk) begin
+  if(rst == 1'b1)
+    d<=0;
+  else 
+    d <= c;
 end
 
 endmodule

openfpga_flow/benchmarks/micro_benchmark/and3_6bits.v

@@ -0,0 +1,20 @@
+/////////////////////////////////////////
+//  Functionality: 2-input AND 
+//  Author:        Xifan Tang
+////////////////////////////////////////
+`timescale 1ns / 1ps
+
+module and2(
+  a,
+  b,
+  c,
+  d);
+
+input wire [5:0] a;
+input wire [5:0] b;
+input wire [5:0] c;
+output wire [5:0] d;
+
+assign d = a & b & c;
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/counter/counter.v

@@ -0,0 +1,16 @@
+module counter(clk, q, rst);
+
+    input clk;
+    input rst;
+    output [7:0] q;
+    reg [7:0] q;
+
+    always @ (posedge clk or negedge rst )
+    begin
+        if(~rst)
+			q <= 8'd0;
+	    else
+		    q <= q + 1;
+    end
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/counter/counter_tb.v

@@ -0,0 +1,24 @@
+module counter_tb;
+
+	reg clk_counter, rst_counter;
+	wire [7:0] q_counter;
+
+	counter_original C_1(
+		clk_counter, 
+		q_counter, 
+		rst_counter);
+
+	initial begin
+		#0 rst_counter = 1'b1; clk_counter = 1'b0;
+		#100 rst_counter = 1'b0;
+	end
+
+	always begin
+		#10 clk_counter = ~clk_counter;
+	end
+
+	initial begin
+		#5000 $stop;
+	end
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/fifo.v

@@ -0,0 +1,118 @@
+module fifo # (parameter abits = 4, dbits = 3)(
+    input clock,
+    input reset,
+    input wr,
+    input rd,
+  input [dbits-1:0] din,
+    output empty,
+    output full,
+  output [dbits-1:0] dout
+    );
+
+wire db_wr, db_rd;
+reg dffw1, dffw2, dffr1, dffr2;
+reg [dbits-1:0] out;
+
+always @ (posedge clock) dffw1 <= wr; 
+always @ (posedge clock) dffw2 <= dffw1;
+
+assign db_wr = ~dffw1 & dffw2; //monostable multivibrator to detect only one pulse of the button
+
+always @ (posedge clock) dffr1 <= rd;
+always @ (posedge clock) dffr2 <= dffr1;
+
+assign db_rd = ~dffr1 & dffr2; //monostable multivibrator to detect only one pulse of the button
+
+
+reg [dbits-1:0] regarray[2**abits-1:0]; //number of words in fifo = 2^(number of address bits)
+reg [abits-1:0] wr_reg, wr_next, wr_succ; //points to the register that needs to be written to
+reg [abits-1:0] rd_reg, rd_next, rd_succ; //points to the register that needs to be read from
+reg full_reg, empty_reg, full_next, empty_next;
+
+assign wr_en = db_wr & ~full; //only write if write signal is high and fifo is not full
+
+//always block for write operation
+always @ (posedge clock)
+ begin
+  if(wr_en)
+   regarray[wr_reg] <= din;  //at wr_reg location of regarray store what is given at din
+
+ end
+
+//always block for read operation
+always @ (posedge clock)
+ begin
+  if(db_rd)
+   out <= regarray[rd_reg];
+ end
+
+
+always @ (posedge clock or posedge reset)
+ begin
+  if (reset)
+   begin
+   wr_reg <= 0;
+   rd_reg <= 0;
+   full_reg <= 1'b0;
+   empty_reg <= 1'b1;
+   end
+
+  else
+   begin
+   wr_reg <= wr_next; //created the next registers to avoid the error of mixing blocking and non blocking assignment to the same signal
+   rd_reg <= rd_next;
+   full_reg <= full_next;
+   empty_reg <= empty_next;
+   end
+ end
+
+always @(*)
+ begin
+  wr_succ = wr_reg + 1; //assigned to new value as wr_next cannot be tested for in same always block
+  rd_succ = rd_reg + 1; //assigned to new value as rd_next cannot be tested for in same always block
+  wr_next = wr_reg;  //defaults state stays the same
+  rd_next = rd_reg;  //defaults state stays the same
+  full_next = full_reg;  //defaults state stays the same
+  empty_next = empty_reg;  //defaults state stays the same
+
+   case({db_wr,db_rd})
+    //2'b00: do nothing LOL..
+
+    2'b01: //read
+     begin
+      if(~empty) //if fifo is not empty continue
+       begin
+        rd_next = rd_succ;
+        full_next = 1'b0;
+       if(rd_succ == wr_reg) //all data has been read
+         empty_next = 1'b1;  //its empty again
+       end
+     end
+
+    2'b10: //write
+     begin
+
+      if(~full) //if fifo is not full continue
+       begin
+        wr_next = wr_succ;
+        empty_next = 1'b0;
+        if(wr_succ == (2**abits-1)) //all registers have been written to
+         full_next = 1'b1;   //its full now
+       end
+     end
+
+    2'b11: //read and write
+     begin
+      wr_next = wr_succ;
+      rd_next = rd_succ;
+     end
+     //no empty or full flag will be checked for or asserted in this state since data is being written to and read from together it can  not get full in this state.
+    endcase
+
+
+ end
+
+assign full = full_reg;
+assign empty = empty_reg;
+assign dout = out;
+endmodule

openfpga_flow/benchmarks/micro_benchmark/output_pattern/output_pattern.v

@@ -0,0 +1,17 @@
+module output_pattern(
+  input data_in,    // input data
+  output reg [126:0] data_out // output data
+);
+
+reg [6:0] index = 0;  // initialize index to 0
+reg [126:0] pattern_1 = 127'b1010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101;  // pattern for when data_in is 1
+reg [126:0] pattern_0 = 127'b0101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010101010;  // pattern for when data_in is 0
+
+always @(*) begin
+  if (data_in == 1)  // if input is 1, output pattern_1
+    data_out = pattern_1[126:0];
+  else              // if input is 0, output pattern_0
+    data_out = pattern_0[126:0];
+end
+
+endmodule

openfpga_flow/benchmarks/micro_benchmark/shift_reg.v

@@ -0,0 +1,35 @@
+module shift_reg(
+    input clock,
+    input reset,
+    input [1:0] control,
+    input in,
+    output [7:0] out
+    );
+
+reg [7:0] r_reg, r_next; //a 7 bit shift register which will be output as is, this can be changed to any size
+
+always @ (posedge clock or posedge reset)
+begin
+ if(reset)
+  r_reg <= 0;
+ else
+  r_reg <= r_next;
+end
+
+always @ (*)
+begin
+
+ if(control[0]) //shift right
+  r_next = {in, r_reg[7:1]};
+
+ else if(control[1]) //shift left
+  r_next = {r_reg[6:0], in};
+
+ else
+  r_next = r_reg; //default state stays the same
+
+end
+
+assign out = r_reg;
+
+endmodule