Toolbox for creating a bonding diagram in Cadence Virtuoso.
This toolbox is used for creating bonding diagrams at Electronics & Drives.
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Create the new library PACKAGES and reference(!) it on your PDK technology library.
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Go in the CIW to Tools > Technology File Manager and press the button Load.... As a result, the Load Technology File form will open. Reference the ASCII Technology file packages.tf from this repository and Merge it with the library PACKAGES (see screenshot below). Confirm with OK.
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Go in the CIW to Tools> Technology File Manager, select the library PACKAGES and press the button Save... . As a result, the Save Technology File form will open. Select the library PACKAGES and confirm with OK.
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Go in the CIW to Tools> Display Resource Manager and press the Merge.... As a result, the Merge Display Resource Files(DRF) form will open. Choose the .drf from your PDK by clicking on the corresponding elements in the From Library box (gpdk045/display.drf in the screenshot below). This .drf file is added to the list Merge DRF Files in sequence. As a second step, provide the file packages.drf from this repository to the From file box and push the button Add.
Provide the name of the merged .drf to the field Destination DRF (display_merged.drf). Make sure that this .drf is loaded at the startup of Virtuoso. It is recommended to add the command
drLoadDrf("display_merged.drf")to your.cdsinit.
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Go to the CIW and load the file packages.il from the repository. You must load this code only once. Reloading is only needed when the packages (i.e., the file packages.il) are updated.
(load "packages.il")
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Load the file bondtools.il from the repository in your
.cdsinit.(load "bondtools.il")
You can create a menu item in the layout editor with
(load "bondtoolsMenu.il")
The following layers are defined by this toolbox:
| Layer Name | Purpose Name | Layer No. | Purpose No. | Description |
|---|---|---|---|---|
| PACKAGE_METALIZATION | drawing | 133 | 0 | metalization in package |
| PACKAGE_LABEL | label | 134 | 0 | labels for leadframe pins |
| BONDWIRE | drawing | 135 | 0 | bondwire |
| BALL | label | 136 | 0 | position of the ball of a bondwire |
| WEDGE | label | 137 | 0 | position of the wedge of a bondwire |
| DEF_CHIP | drawing | 138 | 0 | outline of the chip |
| DEF_PAD | drawing | 139 | 0 | bond pads (opening in passivation) |
| DEF_MARK | drawing | 140 | 0 | markings (noticeable layout structures) |
| PACKAGE_OUTLINE | drawing | 171 | 0 | outline of the package |
A bondwire can be defined by placing two labels with same name in the VLS (Virtuoso Layout Suite). The first label must be placed on the bondpad and the second label must be placed on the lead.
The ending type of bond can be specified using the layer (BALL label or WEDGE label).
The function EDbondtoolsDrawWires must be invoked in the Command Interpreter Window (CIW) to draw the bondwires.
(EDbondtoolsDrawWires
cv
fBallRadius
fWireDiameter
fWedgeExtension
sLogfile
) => t/nilThe parameters of the function are
cv
Cellview where the bondwires are created.
You can reference the cellview in the foreground window with
(geGetWindowCellView) or (gwc).
fBallRadius
Radius of a ball.
fWireDiameter
Diameter of the bondwire.
fWedgeExtension
Wedge extension.
sLogfile
Path to the logfile. No logfile is created when nil is provided
The GUI of the tool can be invoked from the menu bar of the VLS. Go to the element Bondtools and click on Draw Bondwires. As a result, a GUI is shown:
Another way to open the GUI is to execute the
command (EDbondtoolsOpenUserInterface) in the CIW.
Specify the parameters in the GUI and create the bondwires with OK or Apply.
An example of the bonding diagram of a multi-chip die is shown in the screenshots below.
You can export the bondplan as GDS2 using the provided strmInOut.layermap. To export the bondplan go in menu bar of the CIW to
File > Export > Stream...
As a result, the XStream Out form will open.
Provide first the name of the GDS (myBondplan.gds on the example above) and secondly lib/cell/view of the bondplan (Bondplans/myBondplan/layout in the example above). As a last configuration step, please provide strmInOut.layermap from this repository as Layer Map. Push the button Translate or Apply to generate the GDS.
Another options is to export a tikzpicture with ml2TikZ. Use the file layers.tex for this purpose.
The packages stated below are provided in the library PACKAGES.
| Cell Name | Lead Count | Die Cavity (AxB) | Drawing Number |
|---|---|---|---|
| JLCC_44_PB_F86315 | 44 | 0.34x0.34 | PB-F86315 |
| JLCC_68_PB_F86764 | 68 | 0.4x0.4 | PB-F86764 |
The 'packages' in this section correspond to Chip-On-Board (COB) designs used at Electronics & Drives.
| Cell Name | Lead Count |
|---|---|
| ED60_V1 | 60 |
| ED60_V2 | 60 |
| Acronym | Description |
|---|---|
| DIL | Dual-in-line |
| CSOIC | Ceramic Small Outline Integrated Circuit |
| CLCC | C-Leadless Chip Carriers |
| JLCC | J-Leaded Ceramic Chip Carrier |
| CPGA | Ceramic Pin Grid Array |
| SOIC | Small Outline Integrated Circuit |
| QFN | Quad-Flat No-leads |
| CSOP | Ceramic Small Outline Package |
| CDIP | Ceramic Dual Inline Package |
| CQFP | Ceramic Quad Flat Package |
| CPGA | Ceramic Pin Grid Array |
| CQFN | Ceramic Quad Flat Non-Leaded |
| CQFJ | Ceramic Quad Flat J-Leaded |
Copyright (c) 2023 Reutlingen University, Electronics & Drives
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