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How to RUN size and speed scripts to get benchmark on RISC-V GCC toolchain
#206
opened Oct 15, 2024 by
RRArinc
Embench 2.0: Missing Depthconv benchmark's reference platform baseline data.
#202
opened Jun 2, 2024 by
madhu2000u
Tarfind isn't portable due to assuming struct layout
bug
Something isn't working
#186
opened Nov 7, 2023 by
widlarizer
How to run embench on qemu for RISC-V?
help wanted
Extra attention is needed
#185
opened Nov 5, 2023 by
RamNalamothu
Remove I/O dependencies of md5sum benchmark
bug
Something isn't working
#177
opened Feb 20, 2023 by
jeremybennett
Discussing potential advantages of unaligned access and bi-endian hardware support
#174
opened Jan 22, 2023 by
jeras
crc32 size increases is we specify a frequency with --cpu-mhz different from 1 MHz
bug
Something isn't working
#163
opened Jun 21, 2022 by
PaoloS02
In the st benchmark some toolchains hoisting/removing the computation from the benchmarking loop
#161
opened May 16, 2022 by
MarkHillHuawei
In nbody some toolchains hoisting bodies_energy out of main loop
#160
opened May 12, 2022 by
MarkHillHuawei
Proposal: Mechanism for *per-benchmark* iteration control and to clarify the purpose of cpu-mhz
#135
opened Apr 19, 2021 by
Roger-Shepherd
doc/README.md doesn't generate html header defining the character set
#129
opened Apr 7, 2021 by
Roger-Shepherd
malloc_beebs does not ensure correct alignment of allocated objects
#116
opened Mar 15, 2021 by
edward-jones
[Major Need] Proper Documentation of README for CONTRIBUTION
#114
opened Mar 10, 2021 by
ArchishmanSengupta
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