fix(espefuse): Fix efuse base addr for esp32c5 MP

espressif · Apr 19, 2024 · 248dc9a · 248dc9a
1 parent d2bfaad
commit 248dc9a
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Showing 2 changed files with 3 additions and 1 deletion.
diff --git a/espefuse/efuse/esp32c5/mem_definition.py b/espefuse/efuse/esp32c5/mem_definition.py
@@ -20,7 +20,7 @@ class EfuseDefineRegisters(EfuseRegistersBase):
     EFUSE_MEM_SIZE = 0x01FC + 4
 
     # EFUSE registers & command/conf values
-    DR_REG_EFUSE_BASE = 0x600B0800
+    DR_REG_EFUSE_BASE = 0x600B4800
     EFUSE_PGM_DATA0_REG = DR_REG_EFUSE_BASE
     EFUSE_CHECK_VALUE0_REG = DR_REG_EFUSE_BASE + 0x020
     EFUSE_CLK_REG = DR_REG_EFUSE_BASE + 0x1C8

diff --git a/esptool/targets/esp32c5.py b/esptool/targets/esp32c5.py
@@ -13,6 +13,8 @@ class ESP32C5ROM(ESP32C6ROM):
     CHIP_NAME = "ESP32-C5"
     IMAGE_CHIP_ID = 23
 
+    EFUSE_BASE = 0x600B4800
+
     IROM_MAP_START = 0x42000000
     IROM_MAP_END = 0x42800000
     DROM_MAP_START = 0x42800000