Xtensa patches (18.x) (Do not merge, PR created for easier review only) #94
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Implement Debug, DFPAccel, S32C1I, THREADPTR, Extended L32R, ATOMCTL, MEMCTL features.
Implement Exception, HighPriInterrupts, Coprocessor, Interrupt, RelocatableVector, TimerInt, PRID, RegionProtection and MiscSR features. Implement instructions for Exception, Interrupt and RegionProtection features with tests.
Make ESP32 default subtarget.
Implement subtarget dependent SR and UR register parsing and disassembling, add tests. Implement User Registers read/write instructions and add tests.
Implement Xtensa specific streamer to support emit literals.
Implement special processing of MOVI and L32R instructions in assembler parser. The MOVI assembler expression now can have 32-bit immediate values, so also correct xtensa-invalid.s test. Also implement computation of CFA during XtensaMCAsmInfo creation.
Use Multilib class functionality to choose between library variants, based on the command line args.
Add FP instructions test, format FP instruction descriptions.
Remove register class for boolean operands, because it is only suitable for FP compare operations and may lead to problems in other cases. Disable load width reduction, because for IRAM memory it may cause exceptions.
Do not use Frame Pointer by default. Also improve storing function argument from a7 register to a8 register. Corrected funnel shift test.
It was changed in LLVM 18
ambiguities between x24 and format_32 encoding.
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This matches GCC. Partially addresses llvm#115964 Pull Request: llvm#115967
It fixes crash in Xtensa AsmParser::run() during ModuleSummaryIndexAnalysis pass.
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Close in favor of #109 |
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