Skip to content

Commit

Permalink
fix basic import errors
Browse files Browse the repository at this point in the history
  • Loading branch information
yamaguchi1024 committed Jan 6, 2025
1 parent f2f9481 commit a8a0bab
Show file tree
Hide file tree
Showing 10 changed files with 22 additions and 2,483 deletions.
4 changes: 2 additions & 2 deletions src/exo/API.py
Original file line number Diff line number Diff line change
Expand Up @@ -17,8 +17,8 @@
from .frontend.parse_fragment import parse_fragment
from .frontend.pattern_match import match_pattern
from .core.prelude import *
from .rewrite.new_eff import Check_Aliasing
from .dataflow import dataflow_analysis
from .rewrite.analysis import Check_Aliasing
from .rewrite.dataflow import dataflow_analysis

# Moved to new file
from .core.proc_eqv import decl_new_proc, derive_proc, assert_eqv_proc, check_eqv_proc
Expand Down
2 changes: 1 addition & 1 deletion src/exo/backend/parallel_analysis.py
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
from ..core.LoopIR import LoopIR, LoopIR_Rewrite

from ..rewrite.new_eff import Check_ParallelizeLoop
from ..rewrite.analysis import Check_ParallelizeLoop


class ParallelAnalysis(LoopIR_Rewrite):
Expand Down
2 changes: 1 addition & 1 deletion src/exo/rewrite/LoopIR_unification.py
Original file line number Diff line number Diff line change
Expand Up @@ -18,7 +18,7 @@
)
from .LoopIR_scheduling import SchedulingError
from ..core.prelude import *
from .new_eff import Check_Aliasing
from .analysis import Check_Aliasing
import exo.core.internal_cursors as ic


Expand Down
File renamed without changes.
26 changes: 13 additions & 13 deletions src/exo/dataflow.py → src/exo/rewrite/dataflow.py
Original file line number Diff line number Diff line change
Expand Up @@ -5,11 +5,11 @@
from typing import Mapping, Any
from asdl_adt import ADT, validators

from .builtins import BuiltIn
from .configs import Config
from .memory import Memory
from .prelude import Sym, SrcInfo, extclass
from .LoopIR import (
from ..core.extern import Extern
from ..core.configs import Config
from ..core.memory import Memory
from ..core.prelude import Sym, SrcInfo, extclass
from ..core.LoopIR import (
LoopIR,
Alpha_Rename,
SubstArgs,
Expand Down Expand Up @@ -70,7 +70,7 @@ def validateAbsEnv(obj):
| Const( object val )
| USub( expr arg ) -- i.e. -(...)
| BinOp( binop op, expr lhs, expr rhs )
| BuiltIn( builtin f, expr* args )
| Extern( extern f, expr* args )
| StrideExpr( sym name, int dim )
attributes( type type, srcinfo srcinfo )
Expand All @@ -91,7 +91,7 @@ def validateAbsEnv(obj):
ext_types={
"name": validators.instance_of(Identifier, convert=True),
"sym": Sym,
"builtin": BuiltIn,
"extern": Extern,
"binop": validators.instance_of(Operator, convert=True),
"absenv": validateAbsEnv,
"srcinfo": SrcInfo,
Expand Down Expand Up @@ -481,9 +481,9 @@ def map_e(self, e):
df_rhs = self.map_e(e.rhs)
return DataflowIR.BinOp(e.op, df_lhs, df_rhs, self.map_t(e.type), e.srcinfo)

elif isinstance(e, LoopIR.BuiltIn):
elif isinstance(e, LoopIR.Extern):
df_args = self.map_exprs(e.args)
return DataflowIR.BuiltIn(e.f, df_args, self.map_t(e.type), e.srcinfo)
return DataflowIR.Extern(e.f, df_args, self.map_t(e.type), e.srcinfo)

elif isinstance(e, LoopIR.USub):
df_arg = self.map_e(e.arg)
Expand Down Expand Up @@ -1608,8 +1608,8 @@ def fix_expr(self, e: DataflowIR.expr) -> D.val:
return self.abs_usub(e)
elif isinstance(e, DataflowIR.BinOp):
return self.abs_binop(e)
elif isinstance(e, DataflowIR.BuiltIn):
return self.abs_builtin(e)
elif isinstance(e, DataflowIR.Extern):
return self.abs_extern(e)
elif isinstance(e, DataflowIR.StrideExpr):
return self.abs_stride_expr(e)
else:
Expand Down Expand Up @@ -1666,7 +1666,7 @@ def abs_usub(self, e):
pass

@abstractmethod
def abs_builtin(self, e):
def abs_extern(self, e):
# Implement transfer function abstraction for built-ins
pass

Expand Down Expand Up @@ -1718,5 +1718,5 @@ def abs_binop(self, e) -> D:
def abs_usub(self, e) -> D:
return D.SubVal(V.Top())

def abs_builtin(self, e):
def abs_extern(self, e):
return D.SubVal(V.Top())
Original file line number Diff line number Diff line change
@@ -1,6 +1,6 @@
from .dataflow import DataflowIR, D, V
from .LoopIR_pprint import op_prec
from .prelude import Sym, SrcInfo, extclass
from ..core.LoopIR_pprint import op_prec
from ..core.prelude import Sym, SrcInfo, extclass
from collections import ChainMap
from dataclasses import dataclass, field

Expand Down
File renamed without changes.
Loading

0 comments on commit a8a0bab

Please sign in to comment.