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Bender.yml
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Bender.yml
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# Copyright 2022 ETH Zurich and University of Bologna.
# Solderpad Hardware License, Version 0.51, see LICENSE for details.
# SPDX-License-Identifier: SHL-0.51
package:
name: cheshire
authors:
- "Nicole Narr <[email protected]>"
- "Christopher Reinwardt <[email protected]>"
- "Paul Scheffler <[email protected]>"
- "Alessandro Ottaviano <[email protected]>"
- "Thomas Benz <[email protected]>"
dependencies:
apb_uart: { git: "https://github.com/pulp-platform/apb_uart.git", version: 0.2.1 }
axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.2 }
axi_llc: { git: "https://github.com/pulp-platform/axi_llc.git", version: 0.2.1 }
axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.2 }
axi_rt: { git: "https://github.com/pulp-platform/axi_rt.git", version: 0.0.0-alpha.7 }
axi_vga: { git: "https://github.com/pulp-platform/axi_vga.git", version: 0.1.3 }
clic: { git: "https://github.com/pulp-platform/clic.git", version: 2.0.0 }
clint: { git: "https://github.com/pulp-platform/clint.git", version: 0.2.0 }
common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.33.0 }
common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.0 }
cva6: { git: "https://github.com/pulp-platform/cva6.git", rev: pulp-v1.0.0 }
iDMA: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.5.1 }
irq_router: { git: "https://github.com/pulp-platform/irq_router.git", version: 0.0.1-beta.1 }
opentitan_peripherals: { git: "https://github.com/pulp-platform/opentitan_peripherals.git", version: 0.4.0 }
register_interface: { git: "https://github.com/pulp-platform/register_interface.git", version: 0.4.4 }
riscv-dbg: { git: "https://github.com/pulp-platform/riscv-dbg.git", version: 0.8.1 }
serial_link: { git: "https://github.com/pulp-platform/serial_link.git", version: 1.1.1 }
unbent: { git: "https://github.com/pulp-platform/unbent.git", version: 0.1.6 }
dram_rtl_sim: { git: "https://github.com/pulp-platform/dram_rtl_sim.git", version: 0.1.1 }
export_include_dirs:
- hw/include
sources:
- hw/future/UsbOhciAxi4.v
- hw/future/spinal_usb_ohci.sv
- hw/bootrom/cheshire_bootrom.sv
- hw/regs/cheshire_reg_pkg.sv
- hw/regs/cheshire_reg_top.sv
- hw/cheshire_pkg.sv
- hw/cheshire_soc.sv
- target: any(simulation, test)
files:
- target/sim/models/s25fs512s.v
- target/sim/models/24FC1025.v
- target/sim/src/vip_cheshire_soc.sv
- target/sim/src/tb_cheshire_pkg.sv
- target/sim/src/fixture_cheshire_soc.sv
- target/sim/src/tb_cheshire_soc.sv
- target: all(fpga, xilinx)
files:
- target/xilinx/src/phy_definitions.svh
- target/xilinx/src/dram_wrapper_xilinx.sv
- target/xilinx/src/fan_ctrl.sv
- target/xilinx/src/cheshire_top_xilinx.sv