Cheshire is a minimal Linux-capable host platform built around the RISC-V CVA6 core. Its goal is to provide a lightweight, configurable, autonomously booting host to systems that need one, from minimal Linux-capable SoCs to manycore compute accelerators.
Cheshire is developed as part of the PULP project, a joint effort between ETH Zurich and the University of Bologna.
- To learn how to build and use Cheshire, see Getting Started.
- To learn about available simulation, FPGA, and ASIC targets, see Targets.
- For detailed information on Cheshire's inner workings, consult the User Manual.
If you are impatient and have all needed dependencies, you can run make all, then start QuestaSim in target/sim/vsim and run a simulation by typing:
set BINARY ../../../sw/tests/helloworld.spm.elf
source compile.cheshire_soc.tcl
source start.cheshire_soc.tcl
run -all
Unless specified otherwise in the respective file headers, all code checked into this repository is made available under a permissive license. All hardware sources and tool scripts are licensed under the Solderpad Hardware License 0.51 (see LICENSE) or compatible licenses. Register file code (e.g. hw/regs/*.sv) is generated by a fork of lowRISC's regtool and licensed under Apache 2.0. The USB OHCI controller (hw/future/UsbOhciAxi4.v) is generated from the SpinalHDL library licensed under the MIT license. All software sources are licensed under Apache 2.0.
If you use Cheshire in your work, you can cite us:
@article{ottaviano2023cheshire,
title = {Cheshire: A Lightweight, Linux-Capable RISC-V Host
Platform for Domain-Specific Accelerator Plug-In},
author = {Alessandro Ottaviano and Thomas Benz and
Paul Scheffler and Luca Benini},
journal = {IEEE Transactions on Circuits and Systems II: Express Briefs},
year = {2023},
volume = {70},
number = {10},
pages = {3777-3781},
doi = {10.1109/TCSII.2023.3289186}
}