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Patch 3 #4

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97c7c3d
Merged official ATT 4.5.91 Source Release
faux123 Jul 29, 2011
a315348
boost OC to 1.16 GHz
faux123 Aug 6, 2011
5c48470
Added new defconfig for official ATT 4591 source code
faux123 Aug 6, 2011
81caa87
Revert "boost OC to 1.16 GHz" (not stable :p )
faux123 Aug 6, 2011
89d5762
Quick hack to throw away any mem=,nvmem=,vmalloc= args in cmdline, to…
eval- Aug 10, 2011
6d19587
woops. mossyiscool=true? what was i thinking ;)
eval- Aug 10, 2011
3518c49
setup.c: fixed stackframe overflow issue. Fixed compiler warnings
faux123 Aug 11, 2011
dd65ea5
Updated defconfig to include universal cmdline patch
faux123 Aug 11, 2011
3dfc173
Revert "setup.c: fixed stackframe overflow issue. Fixed compiler war…
faux123 Aug 11, 2011
1e584ce
Fixed OC bug
faux123 Aug 26, 2011
51b6dec
Updated defconfig for 018 kernel build
faux123 Aug 26, 2011
fe16733
Updated voltage table to allow higher overclocking
faux123 Aug 26, 2011
3455021
Adjusted clock and voltage for 1.3 GHz OC
faux123 Aug 26, 2011
a86a68d
Fixed a minor code error
faux123 Aug 27, 2011
3ccf784
Added more voltage steps and up maximum voltage
faux123 Aug 27, 2011
28d01cb
defconfig regen
faux123 Sep 2, 2011
a4b7df6
Optimized ARM RWSEM algorithm
Oct 21, 2010
aab2b7e
ARM: SMP: remove per_cpu based spinlock in do_IPI()
Mar 10, 2011
c15fdb5
tegra: Halt AVP when entering suspend
rmcc Aug 19, 2011
ad4199e
ARM: tegra: Enable PL310 dynamic clock gating
toddpoynor Feb 16, 2011
5a7ec5b
ARM: tegra: PL310 restore dynamic clock gating on resume
toddpoynor Feb 25, 2011
ebe56bc
rcu: Accelerate callback processing on CPUs not detecting GP end
paulmck Nov 13, 2009
ff99333
Merge fixes from Motorola Photon 4G 4.5.1A-1_SUN-154 release
turl Sep 5, 2011
7d1c502
Added back Stock Voltage (1.00 GHz) due to popular demand.
faux123 Sep 16, 2011
78c7cbe
Added 1.00 GHz as stock and cleaned up unnecessary defines
faux123 Sep 16, 2011
6739587
The current jhash.h implements the lookup2() hash function by Bob Jen…
faux123 Sep 23, 2011
fe9b40f
cpufreq: address the issue with sibling cores forgetting min/max clock
faux123 Sep 23, 2011
ee534fb
[ARM/tegra] RM: Stopped DVFS in PM_SUSPEND_PREPARE.
Nov 26, 2010
1f76745
[ARM/tegra] RM: Disabled 3D power gating in LP1.
Nov 25, 2010
a1b9148
[ARM/tegra] RM: Updated power ungating procedure.
Nov 3, 2010
e3bf51d
ARM: Add SWP/SWPB emulation for ARMv7 processors (v5)
Jul 14, 2010
d5aa82a
the kernel's memcpy and memmove is very inefficient. But the glibc ve…
faux123 Sep 23, 2011
d2dada9
the performance of memcpy and memmove of the general version is very …
faux123 Sep 23, 2011
d51644b
removed two instances of trailing whitespaces
rpears0n Oct 9, 2011
6b129ba
Moved a long comment from lib/crc32.c to Documentation/crc32.txt wher…
rpears0n Oct 9, 2011
737b85e
Replaced the unit test provided in crc32.c, which doesn't have a make…
rpears0n Oct 9, 2011
371dce2
crc32: minor optimizations and cleanup
joakim-tjernlund Dec 15, 2009
cb5ae31
crc32: some minor cleanups
joakim-tjernlund Mar 5, 2010
5efa045
crc32: major optimization
joakim-tjernlund May 24, 2010
ff69ad9
Replace 2D array references by pointer references in loops.
rpears0n Oct 9, 2011
fa107e0
Misc cleanup of lib/crc32.c and related files
rpears0n Oct 9, 2011
89e17d8
Fix __CHECK_ENDIAN__ warnings
rpears0n Oct 9, 2011
65d4d66
crc32: add real 8 bit
rpears0n Oct 9, 2011
08eea37
add slicing-by-8 algorithm to the existing slicing-by-4 algorithm.
faux123 Oct 9, 2011
2cce306
Add two changes that improve the performance of x86 systems
rpears0n Oct 9, 2011
2b6d252
Some final changes
rpears0n Oct 9, 2011
3d3c52b
crc32: Bolt on crc32c
Oct 22, 2011
de8a030
crypto: crc32c should use library implementation
Oct 22, 2011
d9c5e7c
crc32: Add self-test code for crc32c
Oct 22, 2011
c7ede9a
crc32: Select an algorithm via kconfig
Oct 22, 2011
55e8e50
android binder: update to latest AOSP kernel source
faux123 Oct 22, 2011
82830e8
android lowmemorykiller: Update to latest AOSP kernel
faux123 Oct 22, 2011
5274475
OC: push overclock to 1.45 GHz stable
faux123 Oct 23, 2011
858e0ff
defconfig: updated for 021 kernel
faux123 Oct 26, 2011
bd6c00d
patch to 2.6.32.10
faux123 Aug 6, 2011
c782e11
patch to 2.6.32.11
faux123 Aug 6, 2011
96a74fd
patch to 2.6.32.12
faux123 Aug 6, 2011
446a4c6
patch to 2.6.32.13
faux123 Aug 6, 2011
c1fc9fa
patch to 2.6.32.14
faux123 Aug 6, 2011
f4e9c66
patch to 2.6.32.17
faux123 Aug 6, 2011
ae4f5f2
patch to 2.6.32.19
faux123 Aug 6, 2011
0d5aaeb
patch to 2.6.32.20
faux123 Aug 6, 2011
b87f4e2
patch 2.6.32.21
faux123 Aug 6, 2011
342c228
patch to 2.6.32.22
faux123 Aug 6, 2011
e03d366
patch to 2.6.32.23
faux123 Aug 6, 2011
c626337
patch to 2.6.32.25
faux123 Aug 6, 2011
2a0c901
patch to 2.6.32.26
faux123 Aug 6, 2011
82807e3
patch to 2.6.32.27
faux123 Aug 6, 2011
6e1f71b
patch to 2.6.32.28
faux123 Aug 6, 2011
1aed63e
patch to 2.6.32.29
faux123 Aug 6, 2011
8cf1827
patch to 2.6.32.33
faux123 Aug 6, 2011
a52117a
patch to 2.6.32.39
faux123 Aug 6, 2011
c837b46
Fixed compilation error in net/core/dev.c
faux123 Aug 8, 2011
74110e6
rcu: Accelerate grace period if last non-dynticked CPU
paulmck Feb 23, 2010
0dba630
rcu: "Tiny RCU", The Bloatwatch Edition
paulmck Oct 26, 2009
1c36a76
rcu: Do tiny cleanups in rcutiny
Oct 26, 2009
c115c1b
rcu: Eliminate unneeded function wrapping
paulmck Nov 22, 2009
ca43ee0
input: evdev: Add missing wake_lock_destroy
benoitgoby Jan 19, 2011
b9ccef1
Add zram driver
rmcc Apr 28, 2011
be0f888
swap: Add swap slot free callback to block_device_operations
May 17, 2010
1e48213
zram: Fix sparse warnings
Nov 4, 2011
77a3493
Staging:ZRAM: Make default zram allocation configurable via menuconfig
faux123 Nov 5, 2011
fe6ad82
zram: Kernel config option for number of devices
Nov 5, 2011
a35e3a3
zram: Simplify zram disk resizing interface
Nov 5, 2011
9f5291c
zram: Set initial disksize to some default value
Nov 5, 2011
7bf39e1
Staging:zram: Specify default disksize via menuconfig (in bytes)
faux123 Nov 5, 2011
06d48d3
staging:lowmemkiller add Fudgeswap
faux123 Nov 5, 2011
f5297e5
mmc: core: put eMMC in sleep (cmd5) mode before suspend
balajitk Nov 5, 2011
0056a55
PM: wakelocks: Display wakelocks preventing suspend by default
toddpoynor Nov 5, 2011
bc04f2d
arm: Allow CPU-supported unaligned accesses
Apr 18, 2011
bd15ec6
decompressors: add XZ decompressor module
Larhzu Nov 6, 2011
69ca2c1
decompressors: add boot-time XZ support
Larhzu Nov 6, 2011
27918b8
ARM: support XZ compressed kernels
kaloz Nov 6, 2011
5d37f20
From: Sumit Bhattacharya <[email protected]>
sumitkbh Nov 6, 2011
b8cf995
Kernel Patch: 2.6.32.39 -> 2.6.32.40
faux123 Nov 8, 2011
77e8641
kernel patch: 2.6.32.40 -> 2.6.32.41
faux123 Nov 8, 2011
6f356ce
kernel patch: 2.6.32.41 -> 2.6.32.42
faux123 Nov 8, 2011
671f9b4
kernel patch: 2.6.32.42 -> 2.6.32.43
faux123 Nov 8, 2011
ed78b52
kernel patch: 2.6.32.43 -> 2.6.32.44
faux123 Nov 8, 2011
ba6ebc4
kernel patch: 2.6.32.44 -> 2.6.32.45
faux123 Nov 8, 2011
b0afe12
kernel patch: 2.6.32.45 -> 2.6.32.46
faux123 Nov 8, 2011
dc09b34
kernel patch: 2.6.32.46 -> 2.6.32.47
faux123 Nov 8, 2011
3a8b556
irq: fix build error due to missing irq_pm_syscore_resume
Nov 8, 2011
abecebf
mmc:core: revert to pre-2.6.32.40 mmc driver
faux123 Nov 8, 2011
3df99c6
kernel patch: 2.6.32.47 -> 2.6.32.48
faux123 Nov 9, 2011
598297f
rtc alarm: fix bad index when canceling alarms[]
jpa468 Sep 2, 2011
2247ee6
aes1750: Suspend fingerprint sensor earlier
turl Nov 12, 2011
11b6601
PM: wakelocks: Don't report wake up wakelock if suspend aborted
toddpoynor Aug 9, 2011
9315b63
compilation: clean up most warning messages during compile
faux123 Nov 14, 2011
d47b109
sched: don't call task_group() many times in set_task_rq()
avagin Nov 12, 2011
bdbe229
kernel:sched: LOAD_FREQ (4*HZ+61) avoids loadavg Moire
faux123 Nov 13, 2011
3f51317
USB: f_mass_storage: Disable write cache support
Nov 14, 2011
24aec64
Input: introduce MT event slots
rydberg Jul 16, 2010
c980207
input: mt: Break out slots handling
rydberg Nov 27, 2010
448e14e
[PATCH] input: mt: Add hovering distance axis
rydberg Dec 6, 2010
1922801
[PATCH] Input: introduce device properties
rydberg Dec 18, 2010
408d5d8
init/main.c: execute lockdep_init as early as possible
ming1 Nov 20, 2011
af26e74
lockdep: print lock name for lockdep_init_error
ming1 Nov 20, 2011
ff09915
mm/vmalloc.c: eliminate extra loop in pcpu_get_vm_areas error path
Nov 20, 2011
d80b3b7
PM / Suspend: Fix bug in suspend statistics update
Nov 20, 2011
cb973d2
block: limit default readahead size for small devices
Nov 20, 2011
65449f0
cpufreq: fix cpu freq issues
faux123 Nov 21, 2011
821e785
Fix build breakage caused by LZO commits
turl Oct 23, 2011
e6f49ec
defconfig: updated defconfig for 022 kernel
faux123 Nov 21, 2011
f7deded
OC: add 1.3 GHz option
faux123 Nov 21, 2011
4ed040d
Revert "Merge fixes from Motorola Photon 4G 4.5.1A-1_SUN-154 release"
faux123 Nov 23, 2011
3fdf504
Allow a lower cpu voltage when in suspend to save battery life, might…
clemsyn Nov 24, 2011
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4 changes: 4 additions & 0 deletions .gitignore
Original file line number Diff line number Diff line change
Expand Up @@ -25,8 +25,12 @@
*.elf
*.bin
*.gz
*.gzip
*.bz2
*.lzo
*.lzma
*.xzkern
*.xz
*.patch
*.gcno

Expand Down
2 changes: 2 additions & 0 deletions Documentation/00-INDEX
Original file line number Diff line number Diff line change
Expand Up @@ -104,6 +104,8 @@ cpuidle/
- info on CPU_IDLE, CPU idle state management subsystem.
cputopology.txt
- documentation on how CPU topology info is exported via sysfs.
crc32.txt
- brief tutorial on CRC computation
cris/
- directory with info about Linux on CRIS architecture.
crypto/
Expand Down
2 changes: 2 additions & 0 deletions Documentation/arm/00-INDEX
Original file line number Diff line number Diff line change
Expand Up @@ -30,3 +30,5 @@ memory.txt
- description of the virtual memory layout
nwfpe/
- NWFPE floating point emulator documentation
swp_emulation
- SWP/SWPB emulation handler/logging description
27 changes: 27 additions & 0 deletions Documentation/arm/swp_emulation
Original file line number Diff line number Diff line change
@@ -0,0 +1,27 @@
Software emulation of deprecated SWP instruction (CONFIG_SWP_EMULATE)
---------------------------------------------------------------------

ARMv6 architecture deprecates use of the SWP/SWPB instructions, and recommeds
moving to the load-locked/store-conditional instructions LDREX and STREX.

ARMv7 multiprocessing extensions introduce the ability to disable these
instructions, triggering an undefined instruction exception when executed.
Trapped instructions are emulated using an LDREX/STREX or LDREXB/STREXB
sequence. If a memory access fault (an abort) occurs, a segmentation fault is
signalled to the triggering process.

/proc/cpu/swp_emulation holds some statistics/information, including the PID of
the last process to trigger the emulation to be invocated. For example:
---
Emulated SWP: 12
Emulated SWPB: 0
Aborted SWP{B}: 1
Last process: 314
---

NOTE: when accessing uncached shared regions, LDREX/STREX rely on an external
transaction monitoring block called a global monitor to maintain update
atomicity. If your system does not implement a global monitor, this option can
cause programs that perform SWP operations to uncached memory to deadlock, as
the STREX operation will always fail.

183 changes: 183 additions & 0 deletions Documentation/crc32.txt
Original file line number Diff line number Diff line change
@@ -0,0 +1,183 @@
A brief CRC tutorial.

A CRC is a long-division remainder. You add the CRC to the message,
and the whole thing (message+CRC) is a multiple of the given
CRC polynomial. To check the CRC, you can either check that the
CRC matches the recomputed value, *or* you can check that the
remainder computed on the message+CRC is 0. This latter approach
is used by a lot of hardware implementations, and is why so many
protocols put the end-of-frame flag after the CRC.

It's actually the same long division you learned in school, except that
- We're working in binary, so the digits are only 0 and 1, and
- When dividing polynomials, there are no carries. Rather than add and
subtract, we just xor. Thus, we tend to get a bit sloppy about
the difference between adding and subtracting.

Like all division, the remainder is always smaller than the divisor.
To produce a 32-bit CRC, the divisor is actually a 33-bit CRC polynomial.
Since it's 33 bits long, bit 32 is always going to be set, so usually the
CRC is written in hex with the most significant bit omitted. (If you're
familiar with the IEEE 754 floating-point format, it's the same idea.)

Note that a CRC is computed over a string of *bits*, so you have
to decide on the endianness of the bits within each byte. To get
the best error-detecting properties, this should correspond to the
order they're actually sent. For example, standard RS-232 serial is
little-endian; the most significant bit (sometimes used for parity)
is sent last. And when appending a CRC word to a message, you should
do it in the right order, matching the endianness.

ust like with ordinary division, you proceed one digit (bit) at a time.
Each step of the division, division, you take one more digit (bit) of the
dividend and append it to the current remainder. Then you figure out the
appropriate multiple of the divisor to subtract to being the remainder
back into range. In binary, this is easy - it has to be either 0 or 1,
and to make the XOR cancel, it's just a copy of bit 32 of the remainder.

When computing a CRC, we don't care about the quotient, so we can
throw the quotient bit away, but subtract the appropriate multiple of
the polynomial from the remainder and we're back to where we started,
ready to process the next bit.

A big-endian CRC written this way would be coded like:
for (i = 0; i < input_bits; i++) {
multiple = remainder & 0x80000000 ? CRCPOLY : 0;
remainder = (remainder << 1 | next_input_bit()) ^ multiple;
}

Notice how, to get at bit 32 of the shifted remainder, we look
at bit 31 of the remainder *before* shifting it.

But also notice how the next_input_bit() bits we're shifting into
the remainder don't actually affect any decision-making until
32 bits later. Thus, the first 32 cycles of this are pretty boring.
Also, to add the CRC to a message, we need a 32-bit-long hole for it at
the end, so we have to add 32 extra cycles shifting in zeros at the
end of every message,

These details lead to a standard trick: rearrange merging in the
next_input_bit() until the moment it's needed. Then the first 32 cycles
can be precomputed, and merging in the final 32 zero bits to make room
for the CRC can be skipped entirely. This changes the code to:

for (i = 0; i < input_bits; i++) {
remainder ^= next_input_bit() << 31;
multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
remainder = (remainder << 1) ^ multiple;
}

With this optimization, the little-endian code is particularly simple:
for (i = 0; i < input_bits; i++) {
remainder ^= next_input_bit();
multiple = (remainder & 1) ? CRCPOLY : 0;
remainder = (remainder >> 1) ^ multiple;
}

The most significant coefficient of the remainder polynomial is stored
in the least significant bit of the binary "remainder" variable.
The other details of endianness have been hidden in CRCPOLY (which must
be bit-reversed) and next_input_bit().

As long as next_input_bit is returning the bits in a sensible order, we don't
*have* to wait until the last possible moment to merge in additional bits.
We can do it 8 bits at a time rather than 1 bit at a time:
for (i = 0; i < input_bytes; i++) {
remainder ^= next_input_byte() << 24;
for (j = 0; j < 8; j++) {
multiple = (remainder & 0x80000000) ? CRCPOLY : 0;
remainder = (remainder << 1) ^ multiple;
}
}

Or in little-endian:
for (i = 0; i < input_bytes; i++) {
remainder ^= next_input_byte();
for (j = 0; j < 8; j++) {
multiple = (remainder & 1) ? CRCPOLY : 0;
remainder = (remainder >> 1) ^ multiple;
}
}

If the input is a multiple of 32 bits, you can even XOR in a 32-bit
word at a time and increase the inner loop count to 32.

You can also mix and match the two loop styles, for example doing the
bulk of a message byte-at-a-time and adding bit-at-a-time processing
for any fractional bytes at the end.

To reduce the number of conditional branches, software commonly uses
the byte-at-a-time table method, popularized by Dilip V. Sarwate,
"Computation of Cyclic Redundancy Checks via Table Look-Up", Comm. ACM
v.31 no.8 (August 1998) p. 1008-1013.

Here, rather than just shifting one bit of the remainder to decide
in the correct multiple to subtract, we can shift a byte at a time.
This produces a 40-bit (rather than a 33-bit) intermediate remainder,
and the correct multiple of the polynomial to subtract is found using
a 256-entry lookup table indexed by the high 8 bits.

(The table entries are simply the CRC-32 of the given one-byte messages.)

When space is more constrained, smaller tables can be used, e.g. two
4-bit shifts followed by a lookup in a 16-entry table.

It is not practical to process much more than 8 bits at a time using this
technique, because tables larger than 256 entries use too much memory and,
more importantly, too much of the L1 cache.

To get higher software performance, a "slicing" technique can be used.
See "High Octane CRC Generation with the Intel Slicing-by-8 Algorithm",
ftp://download.intel.com/technology/comms/perfnet/download/slicing-by-8.pdf

This does not change the number of table lookups, but does increase
the parallelism. With the classic Sarwate algorithm, each table lookup
must be completed before the index of the next can be computed.

A "slicing by 2" technique would shift the remainder 16 bits at a time,
producing a 48-bit intermediate remainder. Rather than doing a single
lookup in a 65536-entry table, the two high bytes are looked up in
two different 256-entry tables. Each contains the remainder required
to cancel out the corresponding byte. The tables are different because the
polynomials to cancel are different. One has non-zero coefficients from
x^32 to x^39, while the other goes from x^40 to x^47.

Since modern processors can handle many parallel memory operations, this
takes barely longer than a single table look-up and thus performs almost
twice as fast as the basic Sarwate algorithm.

This can be extended to "slicing by 4" using 4 256-entry tables.
Each step, 32 bits of data is fetched, XORed with the CRC, and the result
broken into bytes and looked up in the tables. Because the 32-bit shift
leaves the low-order bits of the intermediate remainder zero, the
final CRC is simply the XOR of the 4 table look-ups.

But this still enforces sequential execution: a second group of table
look-ups cannot begin until the previous groups 4 table look-ups have all
been completed. Thus, the processor's load/store unit is sometimes idle.

To make maximum use of the processor, "slicing by 8" performs 8 look-ups
in parallel. Each step, the 32-bit CRC is shifted 64 bits and XORed
with 64 bits of input data. What is important to note is that 4 of
those 8 bytes are simply copies of the input data; they do not depend
on the previous CRC at all. Thus, those 4 table look-ups may commence
immediately, without waiting for the previous loop iteration.

By always having 4 loads in flight, a modern superscalar processor can
be kept busy and make full use of its L1 cache.

Two more details about CRC implementation in the real world:

Normally, appending zero bits to a message which is already a multiple
of a polynomial produces a larger multiple of that polynomial. Thus,
a basic CRC will not detect appended zero bits (or bytes). To enable
a CRC to detect this condition, it's common to invert the CRC before
appending it. This makes the remainder of the message+crc come out not
as zero, but some fixed non-zero value. (The CRC of the inversion
pattern, 0xffffffff.)

The same problem applies to zero bits prepended to the message, and a
similar solution is used. Instead of starting the CRC computation with
a remainder of 0, an initial remainder of all ones is used. As long as
you start the same way on decoding, it doesn't make a difference.

5 changes: 1 addition & 4 deletions Documentation/filesystems/proc.txt
Original file line number Diff line number Diff line change
Expand Up @@ -176,7 +176,6 @@ read the file /proc/PID/status:
CapBnd: ffffffffffffffff
voluntary_ctxt_switches: 0
nonvoluntary_ctxt_switches: 1
Stack usage: 12 kB

This shows you nearly the same information you would get if you viewed it with
the ps command. In fact, ps uses the proc file system to obtain its
Expand Down Expand Up @@ -230,7 +229,6 @@ Table 1-2: Contents of the statm files (as of 2.6.30-rc7)
Mems_allowed_list Same as previous, but in "list format"
voluntary_ctxt_switches number of voluntary context switches
nonvoluntary_ctxt_switches number of non voluntary context switches
Stack usage: stack usage high water mark (round up to page size)
..............................................................................

Table 1-3: Contents of the statm files (as of 2.6.8-rc3)
Expand Down Expand Up @@ -309,7 +307,7 @@ address perms offset dev inode pathname
08049000-0804a000 rw-p 00001000 03:00 8312 /opt/test
0804a000-0806b000 rw-p 00000000 00:00 0 [heap]
a7cb1000-a7cb2000 ---p 00000000 00:00 0
a7cb2000-a7eb2000 rw-p 00000000 00:00 0 [threadstack:001ff4b4]
a7cb2000-a7eb2000 rw-p 00000000 00:00 0
a7eb2000-a7eb3000 ---p 00000000 00:00 0
a7eb3000-a7ed5000 rw-p 00000000 00:00 0
a7ed5000-a8008000 r-xp 00000000 03:00 4222 /lib/libc.so.6
Expand Down Expand Up @@ -345,7 +343,6 @@ is not associated with a file:
[stack] = the stack of the main process
[vdso] = the "virtual dynamic shared object",
the kernel system call handler
[threadstack:xxxxxxxx] = the stack of the thread, xxxxxxxx is the stack size

or if empty, the mapping is anonymous.

Expand Down
6 changes: 5 additions & 1 deletion Documentation/filesystems/tmpfs.txt
Original file line number Diff line number Diff line change
Expand Up @@ -82,11 +82,13 @@ tmpfs has a mount option to set the NUMA memory allocation policy for
all files in that instance (if CONFIG_NUMA is enabled) - which can be
adjusted on the fly via 'mount -o remount ...'

mpol=default prefers to allocate memory from the local node
mpol=default use the process allocation policy
(see set_mempolicy(2))
mpol=prefer:Node prefers to allocate memory from the given Node
mpol=bind:NodeList allocates memory only from nodes in NodeList
mpol=interleave prefers to allocate from each node in turn
mpol=interleave:NodeList allocates from each node of NodeList in turn
mpol=local prefers to allocate memory from the local node

NodeList format is a comma-separated list of decimal numbers and ranges,
a range being two hyphen-separated decimal numbers, the smallest and
Expand Down Expand Up @@ -134,3 +136,5 @@ Author:
Christoph Rohland <[email protected]>, 1.12.01
Updated:
Hugh Dickins, 4 June 2007
Updated:
KOSAKI Motohiro, 16 Mar 2010
4 changes: 1 addition & 3 deletions Documentation/hwmon/ltc4245
Original file line number Diff line number Diff line change
Expand Up @@ -72,9 +72,7 @@ in6_min_alarm 5v output undervoltage alarm
in7_min_alarm 3v output undervoltage alarm
in8_min_alarm Vee (-12v) output undervoltage alarm

in9_input GPIO #1 voltage data
in10_input GPIO #2 voltage data
in11_input GPIO #3 voltage data
in9_input GPIO voltage data

power1_input 12v power usage (mW)
power2_input 5v power usage (mW)
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3 changes: 2 additions & 1 deletion Documentation/i2c/busses/i2c-i801
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,8 @@ Supported adapters:
* Intel 82801I (ICH9)
* Intel EP80579 (Tolapai)
* Intel 82801JI (ICH10)
* Intel PCH
* Intel 3400/5 Series (PCH)
* Intel Cougar Point (PCH)
Datasheets: Publicly available at the Intel website

Authors:
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2 changes: 1 addition & 1 deletion Documentation/i2c/instantiating-devices
Original file line number Diff line number Diff line change
Expand Up @@ -100,7 +100,7 @@ static int __devinit usb_hcd_pnx4008_probe(struct platform_device *pdev)
(...)
i2c_adap = i2c_get_adapter(2);
memset(&i2c_info, 0, sizeof(struct i2c_board_info));
strlcpy(i2c_info.name, "isp1301_pnx", I2C_NAME_SIZE);
strlcpy(i2c_info.type, "isp1301_pnx", I2C_NAME_SIZE);
isp1301_i2c_client = i2c_new_probed_device(i2c_adap, &i2c_info,
normal_i2c);
i2c_put_adapter(i2c_adap);
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10 changes: 9 additions & 1 deletion Documentation/input/multi-touch-protocol.txt
Original file line number Diff line number Diff line change
Expand Up @@ -37,7 +37,9 @@ finger or a pen or something else. Devices with more granular information
may specify general shapes as blobs, i.e., as a sequence of rectangular
shapes grouped together by an ABS_MT_BLOB_ID. Finally, for the few devices
that currently support it, the ABS_MT_TRACKING_ID event may be used to
report finger tracking from hardware [5].
report finger tracking from hardware [5]. Devices capable of contact
hovering can use ABS_MT_DISTANCE to indicate the distance between the
contact and the surface.

Here is what a minimal event sequence for a two-finger touch would look
like:
Expand Down Expand Up @@ -87,6 +89,12 @@ the contact. The ratio ABS_MT_TOUCH_MAJOR / ABS_MT_WIDTH_MAJOR approximates
the notion of pressure. The fingers of the hand and the palm all have
different characteristic widths [1].

ABS_MT_DISTANCE

The distance, in surface units, between the contact and the surface. Zero
distance means the contact is touching the surface. A positive number means
the contact is hovering above the surface.

ABS_MT_ORIENTATION

The orientation of the ellipse. The value should describe a signed quarter
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17 changes: 16 additions & 1 deletion Documentation/kernel-parameters.txt
Original file line number Diff line number Diff line change
Expand Up @@ -241,7 +241,7 @@ and is between 256 and 4096 characters. It is defined in the file

acpi_sleep= [HW,ACPI] Sleep options
Format: { s3_bios, s3_mode, s3_beep, s4_nohwsig,
old_ordering, s4_nonvs }
old_ordering, s4_nonvs, sci_force_enable }
See Documentation/power/video.txt for information on
s3_bios and s3_mode.
s3_beep is for debugging; it makes the PC's speaker beep
Expand All @@ -254,6 +254,9 @@ and is between 256 and 4096 characters. It is defined in the file
of _PTS is used by default).
s4_nonvs prevents the kernel from saving/restoring the
ACPI NVS memory during hibernation.
sci_force_enable causes the kernel to set SCI_EN directly
on resume from S1/S3 (which is against the ACPI spec,
but some broken systems don't work without it).

acpi_use_timer_override [HW,ACPI]
Use timer override. For some broken Nvidia NF5 boards
Expand Down Expand Up @@ -875,6 +878,7 @@ and is between 256 and 4096 characters. It is defined in the file
i8042.panicblink=
[HW] Frequency with which keyboard LEDs should blink
when kernel panics (default is 0.5 sec)
i8042.notimeout [HW] Ignore timeout condition signalled by conroller
i8042.reset [HW] Reset the controller during init and cleanup
i8042.unlock [HW] Unlock (ignore) the keylock

Expand Down Expand Up @@ -2574,6 +2578,10 @@ and is between 256 and 4096 characters. It is defined in the file
disables clocksource verification at runtime.
Used to enable high-resolution timer mode on older
hardware, and in virtualized environment.
[x86] noirqtime: Do not use TSC to do irq accounting.
Used to run time disable IRQ_TIME_ACCOUNTING on any
platforms where RDTSC is slow and this accounting
can add overhead.

turbografx.map[2|3]= [HW,JOY]
TurboGraFX parallel port interface
Expand Down Expand Up @@ -2668,6 +2676,13 @@ and is between 256 and 4096 characters. It is defined in the file
medium is write-protected).
Example: quirks=0419:aaf5:rl,0421:0433:rc

userpte=
[X86] Flags controlling user PTE allocations.

nohigh = do not allocate PTE pages in
HIGHMEM regardless of setting
of CONFIG_HIGHPTE.

vdso= [X86,SH]
vdso=2: enable compat VDSO (default with COMPAT_VDSO)
vdso=1: enable VDSO (default)
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