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Ladner-Fisher_adder/carry_operator.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity carry_operator is
+    Port ( propLi : in STD_LOGIC;
+           genrLi : in STD_LOGIC;
+           propHi : in STD_LOGIC;
+           genrHi : in STD_LOGIC;
+           prop_o : out STD_LOGIC;
+           genr_o : out STD_LOGIC);
+end carry_operator;
+
+architecture Behavioral of carry_operator is
+
+begin
+
+    prop_o <= propLi and propHi;
+    genr_o <= genrHi or (genrLi and propHi);
+
+end Behavioral;

Ladner-Fisher_adder/development/LFA16.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity LFA16 is
+    Port ( x : in STD_LOGIC_VECTOR (15 downto 0);
+           y : in STD_LOGIC_VECTOR (15 downto 0);
+           s : out STD_LOGIC_VECTOR (15 downto 0);
+           p, g : out STD_LOGIC_VECTOR (15 downto 0));
+end LFA16;
+
+architecture Behavioral of LFA16 is
+
+    component carry_operator is
+        Port ( propLi : in STD_LOGIC;
+               genrLi : in STD_LOGIC;
+               propHi : in STD_LOGIC;
+               genrHi : in STD_LOGIC;
+               prop_o : out STD_LOGIC;
+               genr_o : out STD_LOGIC);
+    end component;
+
+    component LFA8 is
+        Port ( x : in STD_LOGIC_VECTOR (7 downto 0);
+               y : in STD_LOGIC_VECTOR (7 downto 0);
+               s : out STD_LOGIC_VECTOR (7 downto 0);
+               p, g : out STD_LOGIC_VECTOR (7 downto 0));
+    end component;
+
+    signal xL, xH, yL, yH, sL, sH : std_logic_vector(7 downto 0);
+    signal gi, pi : std_logic_vector(15 downto 0);
+    signal po, go : std_logic_vector(15 downto 8);
+
+begin
+
+xL <= x(7 downto 0);
+yL <= y(7 downto 0);
+xH <= x(15 downto 8);
+yH <= y(15 downto 8);
+
+LFA8_instL : LFA8 port map (xL, yL, sL, pi(7 downto 0), gi(7 downto 0));
+
+LFA8_instH : LFA8 port map (xH, yH, sH, pi(15 downto 8), gi(15 downto 8));
+
+carries_gen : for i in 8 to 15 generate
+carry_op_instances : carry_operator port map(
+    propLi => pi(7),
+    genrLi => gi(7),
+    propHi => pi(i),
+    genrHi => gi(i),
+    prop_o => po(i),
+    genr_o => go(i));
+end generate;
+
+s <= (sH & sL) xor (go(14 downto 8) & gi(7 downto 0) & '0');
+
+g <= go & gi(7 downto 0);
+p <= po & pi(7 downto 0);
+
+end Behavioral;

Ladner-Fisher_adder/development/LFA16test.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_unsigned.all;
+
+entity LFA16test is
+end LFA16test;
+
+architecture Behavioral of LFA16test is
+
+    component LFA16 is
+        Port ( x : in STD_LOGIC_VECTOR (15 downto 0);
+               y : in STD_LOGIC_VECTOR (15 downto 0);
+               s : out STD_LOGIC_VECTOR (15 downto 0);
+               p, g : out STD_LOGIC_VECTOR (15 downto 0));
+    end component;
+
+    signal x : STD_LOGIC_VECTOR (15 downto 0);
+    signal y : STD_LOGIC_VECTOR (15 downto 0);
+    signal s : STD_LOGIC_VECTOR (15 downto 0);
+    signal p, g : STD_LOGIC_VECTOR (15 downto 0);
+    signal test : STD_LOGIC;
+
+begin
+
+dut : LFA16 port map(x, y, s, p, g);
+
+test <= '1' when s = (x + y) else '0';
+
+    process begin
+        x <= x"1121";
+        y <= x"22a1";
+        wait for 1 ns; 
+        x <= x"3322";
+        wait for 1 ns; 
+        x <= x"4423";
+        wait for 1 ns; 
+        x <= x"5524";
+        wait for 1 ns;
+
+        x <= x"6631";
+        y <= x"77b4";
+        wait for 1 ns; 
+        x <= x"8832";
+        wait for 1 ns; 
+        x <= x"9933";
+        wait for 1 ns; 
+        x <= x"aa34";
+        wait for 1 ns;
+
+        x <= x"bb41";
+        y <= x"ccc8";
+        wait for 1 ns; 
+        x <= x"dd42";
+        wait for 1 ns; 
+        x <= x"ee43";
+        wait for 1 ns; 
+        x <= x"ff44";
+        wait for 1 ns;
+
+        x <= x"7f51";
+        y <= x"3dc8";
+        wait for 1 ns; 
+        x <= x"9d75";
+        wait for 1 ns; 
+        x <= x"5b93";
+        wait for 1 ns; 
+        x <= x"fcef";
+        wait for 1 ns;
+
+        x <= "1100010100101001";
+        y <= "0011101011010111";
+        wait for 1 ns;
+        x <= "0010100111000101";
+        y <= "1101011100111010";
+        wait for 1 ns;
+
+        wait; 
+
+    end process;
+
+end Behavioral;

Ladner-Fisher_adder/development/LFA2.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity LFA2 is
+    Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
+           y : in STD_LOGIC_VECTOR (1 downto 0);
+           s : out STD_LOGIC_VECTOR (1 downto 0);
+           p, g : out STD_LOGIC);
+end LFA2;
+
+architecture Behavioral of LFA2 is
+
+    component carry_operator is
+        Port ( propLi : in STD_LOGIC;
+               genrLi : in STD_LOGIC;
+               propHi : in STD_LOGIC;
+               genrHi : in STD_LOGIC;
+               prop_o : out STD_LOGIC;
+               genr_o : out STD_LOGIC);
+    end component;
+
+    signal pi, gi : std_logic_vector(1 downto 0);
+
+begin
+
+s <= x xor y;
+
+pi <= x xor y;  -- xor bc. if bith are 1, the output is 0 again, and it kills the carry
+gi <= x and y;  -- and, bc. if both are 1, a carry is generated at that position
+                -- so a stage either generates or propagates a carry...(*)
+
+carry_op_inst0 : carry_operator port map(
+    propLi => pi(0),
+    genrLi => gi(0),
+    propHi => pi(1),
+    genrHi => gi(1),
+    prop_o => po(1),
+    genr_o => go(1));
+
+end Behavioral;

Ladner-Fisher_adder/development/LFA2test.vhd

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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+use IEEE.std_logic_unsigned.all;
+
+entity LFA2test is
+end LFA2test;
+
+architecture Behavioral of LFA2test is
+
+    component LFA2 is
+        Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
+               y : in STD_LOGIC_VECTOR (1 downto 0);
+               s : out STD_LOGIC_VECTOR (1 downto 0);
+               p, g : out STD_LOGIC);
+    end component;
+
+    signal x : STD_LOGIC_VECTOR (1 downto 0);
+    signal y : STD_LOGIC_VECTOR (1 downto 0);
+    signal s : STD_LOGIC_VECTOR (1 downto 0);
+    signal p, g, test : STD_LOGIC;
+
+begin
+
+dut : LFA2 port map(x, y, s, p, g);
+
+test <= '1' when s = (x + y) else '0';
+
+    process begin
+        x <= "00";
+        y <= "00";
+        wait for 1 ns; 
+        x <= "01";
+        wait for 1 ns; 
+        x <= "10";
+        wait for 1 ns; 
+        x <= "11";
+        wait for 1 ns; 
+
+        x <= "00";
+        y <= "01";
+        wait for 1 ns; 
+        x <= "01";
+        wait for 1 ns; 
+        x <= "10";
+        wait for 1 ns; 
+        x <= "11";
+        wait for 1 ns; 
+
+        x <= "00";
+        y <= "10";
+        wait for 1 ns; 
+        x <= "01";
+        wait for 1 ns; 
+        x <= "10";
+        wait for 1 ns; 
+        x <= "11";
+        wait for 1 ns; 
+
+        x <= "00";
+        y <= "11";
+        wait for 1 ns; 
+        x <= "01";
+        wait for 1 ns; 
+        x <= "10";
+        wait for 1 ns; 
+        x <= "11";
+        wait for 1 ns;
+
+        wait; 
+
+    end process;
+
+end Behavioral;

Ladner-Fisher_adder/development/LFA4.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity LFA4 is
+    Port ( x : in STD_LOGIC_VECTOR (3 downto 0);
+           y : in STD_LOGIC_VECTOR (3 downto 0);
+           s : out STD_LOGIC_VECTOR (3 downto 0);
+           p, g : out std_logic_vector(3 downto 0));
+end LFA4;
+
+architecture Behavioral of LFA4 is
+
+    component carry_operator is
+        Port ( propLi : in STD_LOGIC;
+               genrLi : in STD_LOGIC;
+               propHi : in STD_LOGIC;
+               genrHi : in STD_LOGIC;
+               prop_o : out STD_LOGIC;
+               genr_o : out STD_LOGIC);
+    end component;
+
+    component LFA2 is
+        Port ( x : in STD_LOGIC_VECTOR (1 downto 0);
+               y : in STD_LOGIC_VECTOR (1 downto 0);
+               s : out STD_LOGIC_VECTOR (1 downto 0);
+               p, g : out STD_LOGIC);
+    end component;
+
+    signal xL, xH, yL, yH, sL, sH : std_logic_vector(1 downto 0);
+    signal ci, si : std_logic_vector(3 downto 0);
+    signal pL, gL, pH, gH, p2, g2, pi, gi, g0, g1, pmax, gmax, p0 : std_logic;
+
+begin
+
+xL <= x(1 downto 0);
+yL <= y(1 downto 0);
+xH <= x(3 downto 2);
+yH <= y(3 downto 2);
+
+LFA2_instL : LFA2 port map (xL, yL, sL, pL, gL);
+
+LFA2_instH : LFA2 port map (xH, yH, sH, pH, gH);
+
+g0 <= x(0) and y(0);
+p0 <= x(0) xor y(0);
+g1 <= x(1) and y(1);
+p2 <= x(2) xor y(2);
+g2 <= x(2) and y(2);
+
+carry_op_inst2 : carry_operator port map(
+    propLi => pL,
+    genrLi => gL,
+    propHi => p2,
+    genrHi => g2,
+    prop_o => pi,
+    genr_o => gi);
+
+carry_op_inst3 : carry_operator port map(
+    propLi => pL,
+    genrLi => gL,
+    propHi => pH,
+    genrHi => gH,
+    prop_o => pmax,
+    genr_o => gmax);
+
+si <= sH & sL;
+--ci <= gi & gL & g0 & '0';
+
+s <= si;-- xor ci;
+p <= pmax & pi & pL & p0;
+g <= gmax & gi & gL & g0;
+
+end Behavioral;