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Added pipelining for performance testing
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@fbv81bp
fbv81bp authored Jul 16, 2023
1 parent 2485d14 commit eff4d30
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45 changes: 35 additions & 10 deletions Ladner-Fisher_adder/recursiveLFA_stages.vhd
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Original file line number Diff line number Diff line change
Expand Up @@ -3,7 +3,8 @@ use IEEE.STD_LOGIC_1164.ALL;

entity recursiveLFA_stages is
Generic(width : integer);
Port ( x : in STD_LOGIC_VECTOR (width-1 downto 0);
Port ( --clock : std_logic;
x : in STD_LOGIC_VECTOR (width-1 downto 0);
y : in STD_LOGIC_VECTOR (width-1 downto 0);
s : out STD_LOGIC_VECTOR (width-1 downto 0);
p, g : out STD_LOGIC_VECTOR (width-1 downto 0));
Expand All @@ -13,7 +14,8 @@ architecture Behavioral of recursiveLFA_stages is

component recursiveLFA_stages is
Generic (width : integer);
Port ( x : in STD_LOGIC_VECTOR (width-1 downto 0);
Port ( --clock : std_logic;
x : in STD_LOGIC_VECTOR (width-1 downto 0);
y : in STD_LOGIC_VECTOR (width-1 downto 0);
s : out STD_LOGIC_VECTOR (width-1 downto 0);
p, g : out STD_LOGIC_VECTOR (width-1 downto 0));
Expand Down Expand Up @@ -43,35 +45,58 @@ recursion_condition : if width > 2 generate

LFA_recursion_instL : recursiveLFA_stages
generic map(width/2)
port map (xL, yL, sL, pi(width/2-1 downto 0), gi(width/2-1 downto 0));
port map (--clock,
xL, yL, sL, pi(width/2-1 downto 0), gi(width/2-1 downto 0));

LFA_recursion_instH : recursiveLFA_stages
generic map(width/2)
port map (xH, yH, sH, pi(width-1 downto width/2), gi(width-1 downto width/2));

s <= sH & sL;
port map (--clock,
xH, yH, sH, pi(width-1 downto width/2), gi(width-1 downto width/2));

--testing performance
--process (clock) begin
-- if rising_edge(clock) then
s <= sH & sL;
-- end if;
--end process;
--end of performance test

end generate;

finish_recursion : if width = 2 generate

gi <= x and y;
pi <= x xor y;
s <= pi;


--testing performance
--process (clock) begin
-- if rising_edge(clock) then
s <= pi;
-- end if;
--end process;
--end of performance test

end generate;

carries_gen : for i in width/2 to width-1 generate

carry_op_instances : carry_operator port map(
propLi => pi(width/2-1),
genrLi => gi(width/2-1),
propHi => pi(i),
genrHi => gi(i),
prop_o => po(i),
genr_o => go(i));

end generate;

g <= go & gi(width/2-1 downto 0);
p <= po & pi(width/2-1 downto 0);
--testing performance
--process (clock) begin
-- if rising_edge(clock) then
g <= go & gi(width/2-1 downto 0);
p <= po & pi(width/2-1 downto 0);
-- end if;
--end process;
--end of performance test

end Behavioral;
64 changes: 40 additions & 24 deletions Ladner-Fisher_adder/recursiveLFA_top.vhd
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Original file line number Diff line number Diff line change
@@ -1,30 +1,32 @@
--for testing:
--library IEEE;
--use IEEE.STD_LOGIC_1164.ALL;
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use IEEE.std_logic_unsigned.all;
use IEEE.STD_LOGIC_1164.ALL;
--library IEEE;
--use IEEE.std_logic_1164.all;
--use IEEE.numeric_std.all;
--use IEEE.std_logic_unsigned.all;
--end of testing modifications

entity recursiveLFA_top is
--for testing:
-- Generic(width : integer := 64);
-- Port ( x : in STD_LOGIC_VECTOR (width/2-1 downto 0;
-- y : in STD_LOGIC_VECTOR (width/2-1 downto 0);
-- s : out STD_LOGIC_VECTOR (width/2-1 downto 0));
Generic(width : integer := 64);
Port ( x : in STD_LOGIC_VECTOR (width-1 downto 0) := x"ef123456789adcef";
y : in STD_LOGIC_VECTOR (width-1 downto 0) := x"cb9876543210debb";
s : inout STD_LOGIC_VECTOR (width-1 downto 0));
Port ( --clock : in std_logic;
x : in STD_LOGIC_VECTOR (width-1 downto 0);
y : in STD_LOGIC_VECTOR (width-1 downto 0);
s : out STD_LOGIC_VECTOR (width-1 downto 0));
-- Generic(width : integer := 64);
-- Port ( x : in STD_LOGIC_VECTOR (width-1 downto 0) := x"ef123456789adcef";
-- y : in STD_LOGIC_VECTOR (width-1 downto 0) := x"cb9876543210debb";
-- s : inout STD_LOGIC_VECTOR (width-1 downto 0));
--end of testing modifications
end recursiveLFA_top;

architecture Behavioral of recursiveLFA_top is

component recursiveLFA_stages is
Generic (width : integer);
Port ( x : in STD_LOGIC_VECTOR (width-1 downto 0);
Port ( --clock : std_logic;
x : in STD_LOGIC_VECTOR (width-1 downto 0);
y : in STD_LOGIC_VECTOR (width-1 downto 0);
s : out STD_LOGIC_VECTOR (width-1 downto 0);
p, g : out STD_LOGIC_VECTOR (width-1 downto 0));
Expand All @@ -43,24 +45,32 @@ architecture Behavioral of recursiveLFA_top is
signal gi, pi : std_logic_vector(width-1 downto 0);
signal po, go : std_logic_vector(width-1 downto width/2);

--for testing:
signal test_passed : std_logic;
--for testing:
-- signal test_passed : std_logic;
--end of testing modifications

begin

xL <= x(width/2-1 downto 0);
yL <= y(width/2-1 downto 0);
xH <= x(width-1 downto width/2);
yH <= y(width-1 downto width/2);

--testing performance
--process (clock) begin
-- if rising_edge(clock) then
xL <= x(width/2-1 downto 0);
yL <= y(width/2-1 downto 0);
xH <= x(width-1 downto width/2);
yH <= y(width-1 downto width/2);
-- end if;
--end process;
--end of performance test

LFA_rceursion_instL : recursiveLFA_stages
generic map(width/2)
port map (xL, yL, sL, pi(width/2-1 downto 0), gi(width/2-1 downto 0));
port map (--clock,
xL, yL, sL, pi(width/2-1 downto 0), gi(width/2-1 downto 0));

LFA_rceursion_instH : recursiveLFA_stages
generic map(width/2)
port map (xH, yH, sH, pi(width-1 downto width/2), gi(width-1 downto width/2));
port map (--clock,
xH, yH, sH, pi(width-1 downto width/2), gi(width-1 downto width/2));

carries_gen : for i in width/2 to width-1 generate
carry_op_instances : carry_operator port map(
Expand All @@ -72,10 +82,16 @@ carries_gen : for i in width/2 to width-1 generate
genr_o => go(i));
end generate;

s <= (sH & sL) xor (go(width-2 downto width/2) & gi(width/2-1 downto 0) & '0');
--testing performance
--process (clock) begin
-- if rising_edge(clock) then
s <= (sH & sL) xor (go(width-2 downto width/2) & gi(width/2-1 downto 0) & '0');
-- end if;
--end process;
--end of performance test

--for testing:
test_passed <= '1' when s = x + y else '0';
--test_passed <= '1' when s = x + y else '0';
--end of testing modifications

end Behavioral;

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