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FireSim Vs AWS Upstream Tracking #50

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FireSim Vs AWS Upstream Tracking #50

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ac367d9
start firesim f1 project from prepare_new_cl.sh
sagark Jun 21, 2017
821723c
start from hello world since it\'s closer to what we want
sagark Jun 21, 2017
9e5b074
rename hello_world -> firesim
sagark Jun 21, 2017
0a4b504
WIP connect firesim/midas to f1 top
sagark Jun 21, 2017
5a73770
check in empty F1Shim, this at least builds (xsim appears to be crash…
sagark Jun 21, 2017
f43ac6a
revert to full rocketchip in cl_firesim_generated.sv
sagark Jun 21, 2017
5d30a90
simulator now builds... xsim doesnt like the stuff inside the ifndef …
sagark Jun 22, 2017
c52cd36
solved the crash: xsim can't handle properly, remove them all for now
sagark Jun 22, 2017
72da7b6
hook up DDR interface. this is just for prototyping, only uses 64 bit…
sagark Jun 22, 2017
9c5ca41
fix the hello world C test
sagark Jun 23, 2017
dbbbd7e
getting reasonable starting responses from hardcoded tests
sagark Jun 24, 2017
e3b2c89
slow, but working MidasTop-f1 + xsim. communicating over pipes
sagark Jun 24, 2017
9dae032
fix dr -> ddr
sagark Jun 26, 2017
7f01725
fix master size, add queues, fix simulation
sagark Jun 27, 2017
1117964
runs hello world in xsim with heavy tweaking
sagark Jun 27, 2017
065cc65
Pull in changes for upstream v1.2.4 release
sagark Jun 28, 2017
d81a0db
using dramsim works in xsim, now trying fpga
sagark Jun 29, 2017
a536430
fix ddr request size to enable using fpga mem model. works in both xs…
sagark Jun 29, 2017
94c37e3
emulated backpressure
sagark Jun 30, 2017
7ad6dc8
test for b resp after each write
sagark Jun 30, 2017
6fdabf2
cleanup API between simif and xsim
sagark Jun 30, 2017
7e5bd73
speed up software sim
sagark Jul 1, 2017
261b20f
add .gitignore in cl_firesim
sagark Jul 1, 2017
ff6b498
bump RTL from ec2-pr branch
sagark Jul 2, 2017
05c1549
no more blocking writes
sagark Jul 3, 2017
ab93569
use vivado axi width adapter for 64 bit <-> 512 bit conversion for DDR
sagark Jul 4, 2017
3e8b1b7
generate IDs for reads
sagark Jul 4, 2017
65c3131
gitignore lib dir
sagark Jul 4, 2017
2ce2835
add clock converters for axi, not yet instantiated
sagark Jul 4, 2017
1f4402b
instantiate clock converter on AXI OCL
sagark Jul 4, 2017
33e5eac
runs on the FPGA @ 62 MHz with clock crossings using clock recipe A0
sagark Jul 5, 2017
b67b87a
remove width adapter, this actually works reliably now at 62 MHz
sagark Jul 8, 2017
578dff8
rtl with UART input now supported by UARTWidget
sagark Jul 10, 2017
456c5e6
save utilization reports during runs
sagark Jul 11, 2017
c78b52e
rtl for new rocket-chip
sagark Jul 16, 2017
2ebfa86
bump rtl
sagark Jul 16, 2017
f3d811c
fixed UART rtl, works on fpga
sagark Jul 17, 2017
35e76d9
bump with new output (only name change)
sagark Jul 18, 2017
840da1b
bump to output of scripts
sagark Jul 18, 2017
3101908
simplenic RTL works on fpga
sagark Jul 18, 2017
77a20f7
WIP blockdev
sagark Jul 23, 2017
cdbfa9e
bump after hardcoded width cleanup
sagark Jul 23, 2017
5790d29
Merge branch 'master' of github.com:aws/aws-fpga into 1.3_shell
sagark Jul 31, 2017
f62b66d
update cl_firesim with shell v1.3.0 changes from cl_hello_world
sagark Jul 31, 2017
8bb3eba
add missing v1.2.5 hotfix updates for cl_firesim
sagark Jul 31, 2017
634501f
fix address bit width. looks like it runs perlbench now
sagark Aug 5, 2017
d3489bf
boots linux at 90 MHz. see notes:
sagark Aug 15, 2017
ab66103
default to TIMING strategy
sagark Aug 16, 2017
5d2d3d0
run shim at 250 MHz, default to clock recipe A1
sagark Aug 17, 2017
2ebee77
run xsim again
donggyukim Aug 28, 2017
99db694
Merge pull request #1 from firesim/fix-xsim
sagark Sep 10, 2017
4765e94
Merge branch 'master' of github.com:aws/aws-fpga
sagark Sep 10, 2017
036a930
WIP RTL for new RC bump/move to firechip
sagark Sep 12, 2017
5fbb42b
fix gitignore
sagark Sep 12, 2017
39baf06
works on FPGA, including NIC
sagark Sep 12, 2017
0676496
bump to 85 MHz clock. 90 failed timing barely (but seems to work in p…
sagark Sep 12, 2017
e2464dd
bump with endpoint updates to set mac from host
sagark Sep 13, 2017
26cebb4
bump to latest RTL
sagark Sep 14, 2017
bf8ec7f
working single-core rtl post mem-model-merge (not yet on firesim master)
sagark Sep 24, 2017
a162a8b
Update to upstream aws-fpga 1.3.3. Merge remote-tracking branch 'upst…
sagark Sep 25, 2017
37469f4
singlenode rtl for latest built version, should be equivalent to the …
sagark Sep 25, 2017
26d66b8
Update RTL to match that which would be generated by non-det midas
davidbiancolin Oct 2, 2017
e9c8cb0
Update README.md
sagark Oct 3, 2017
fadbc75
fix endpoint not driving keep field
sagark Oct 5, 2017
d22d604
bump to removed target io hacks
davidbiancolin Oct 6, 2017
a708ee5
expose registers in F1Shim to DMA_PCIS interface directly
sagark Oct 12, 2017
bb0f97a
add sanity check that PCIS is connected properly at top level. requir…
sagark Oct 12, 2017
6929b23
both regular firesim linux boot and edma talking to registers works o…
sagark Oct 12, 2017
ded7ff1
bump to RTL with PCIS pushed into SimpleNICWidget
sagark Oct 12, 2017
2eb8a96
bump to RTL with Queues attached to PCIS in SimpleNICWidget instead o…
sagark Oct 13, 2017
9af5223
queues attached to NIC inputs, add valid check MMIO regs
sagark Oct 14, 2017
3bf7e3e
add counters on outgoing/incoming queues for batching
sagark Oct 14, 2017
ee57a50
first test RTL for 512nic + cycle accurate endpoint
sagark Oct 15, 2017
5595d3f
increase queue depth, fix counters
sagark Oct 17, 2017
7d6b76b
working RTL with 7 64-bit transacts per 512 bit token. also switch to…
sagark Oct 18, 2017
733cb79
working cycle-accurate network
sagark Oct 20, 2017
1ac6ad1
bump rtl
sagark Oct 22, 2017
00d7b4f
rocket-chip bumped rtl
sagark Oct 23, 2017
6c5c83c
nic fix
sagark Oct 24, 2017
9c9cace
update gitignore
sagark Oct 24, 2017
20eb691
fix UARTWidget div, PeripheryBusKey's frequency
sagark Oct 24, 2017
eaf959e
[rtl] nic with hellaqueue
sagark Oct 25, 2017
9679f94
Regenerate the clock generator (190, 175, 160), update rtl
davidbiancolin Oct 20, 2017
ece386c
update rtl with nic, 1.6 GHz, blockdev with >2GB fix
sagark Oct 26, 2017
18cef3b
default to 160 MHz for firesim, icenic / simplenicwidget fail timing …
sagark Oct 26, 2017
405fd5e
single node with uart queue increases, nic queue increases, uart div …
sagark Oct 29, 2017
66f4fb6
merge 1.3.4 from upstream. not yet tested
sagark Dec 2, 2017
e6719cd
start updating cl_firesim internals for 1.3.4, excluding verif direct…
sagark Dec 2, 2017
c6dd436
propagate remaining 1.3.4 changes into verif
sagark Dec 2, 2017
9743692
fix strategy timing, broke again in upstream
sagark Dec 2, 2017
139cb16
bump rtl
sagark Dec 2, 2017
13c9437
fix XSim build (won't run yet, needs DMA_PCIS)
sagark Dec 3, 2017
fb68206
Merge branch 'master' of github.com:aws/aws-fpga
sagark Dec 9, 2017
8f7c9ef
merge upstream patches to 1.3.4
sagark Dec 9, 2017
d94cae6
Support 16GiB target memory systems
davidbiancolin Dec 7, 2017
6f5738e
Revert "Support 16GiB target memory systems"
davidbiancolin Dec 10, 2017
56ca109
no more generated files
donggyukim Jan 29, 2018
a628e8b
no more hacks
donggyukim Jan 29, 2018
b436aa6
Merge branch 'master' of github.com:firesim/aws-fpga-firesim into don…
donggyukim Jan 29, 2018
0059b21
Move simulation defines into makefrags
davidbiancolin Feb 8, 2018
eee0d95
Merge pull request #3 from firesim/donggyu-bump-with-mem-model
davidbiancolin Feb 15, 2018
727cce0
Support 16GiB target memory systems
davidbiancolin Dec 7, 2017
862e00e
reconnect NIC signals
zhemao Mar 10, 2018
34e055f
one clock gen with both sets of clocks that we frequently use (190, 1…
sagark Mar 17, 2018
95420db
xdc adds RAM_STYLE ULTRA property. currently hardcoded path
sagark Mar 20, 2018
2aee32e
Fix transaction packing in width adapter
davidbiancolin Apr 10, 2018
633f297
Fix comments made when i should have been sleeping
davidbiancolin Apr 13, 2018
dee49e3
Merge remote-tracking branch 'upstream/master' into width-adapter-fix…
sagark Apr 18, 2018
1e082ba
apply changes from upstream cl_ example projects to cl_firesim. also …
sagark Apr 18, 2018
ff0faa4
fix TIMING strategy again
sagark Apr 18, 2018
61b58d1
default to 90MHz, since this is what designs with NIC and/or L2 require
sagark Apr 19, 2018
1d910c5
add a .gitignore for cl_FireSim*
sagark Apr 19, 2018
18fae63
Merge tag 'v1.3.8' into bump-aws-fpga-1.3.8
sagark Jul 21, 2018
711fde9
pull in changes from cl_dram_dma to cl_firesim for v1.3.8 bump
sagark Jul 21, 2018
8e32578
Merge tag 'v1.4.0' into bump-aws-fpga-1.4.0
sagark Jul 21, 2018
df5df87
pull in changes from cl_dram_dma to cl_firesim for v1.4.0 bump
sagark Jul 21, 2018
ce370e6
fix constraint that broke during the upgrade
sagark Jul 22, 2018
4dc5186
cleanup git status. add ddr4_rank.sv from shell download and ignore a…
sagark Jul 22, 2018
c06c998
fix xsim simulation (probably not vcs)
sagark Jul 29, 2018
fba90ff
fix vcs FPGA-level simulation
sagark Jul 30, 2018
547a837
Prune an unnecessary timing constraint
davidbiancolin Aug 6, 2018
108d83b
Add false paths to remove recovery failures to reset synchronizers
davidbiancolin Aug 6, 2018
ae4a6c4
Merge pull request #7 from firesim/cut-paths
davidbiancolin Aug 8, 2018
29fb499
tie off/attach new ddr/pcis signals
sagark Aug 11, 2018
5771530
fix .gitignore for FireBOOM
sagark Aug 11, 2018
bc04978
Merge pull request #8 from firesim/connect-new-signals
sagark Aug 12, 2018
696e95d
Update README.md
sagark Aug 12, 2018
3e4cd2f
Merge pull request #10 from firesim/fix-readme
sagark Aug 12, 2018
2a33b4e
Merge pull request #9 from firesim/dev
sagark Aug 13, 2018
783d3f5
auto-ila base
alonamid Sep 7, 2018
ebf5db9
Merge pull request #11 from firesim/auto-ila
sagark Sep 20, 2018
bca30e6
Merge pull request #12 from firesim/dev
sagark Sep 22, 2018
e9cac2f
add DDR channels
alonamid Nov 4, 2018
98ee779
fix synthesis script
alonamid Nov 8, 2018
bf64f7b
uram contraint
alonamid Nov 28, 2018
c6e1079
add stuff to xsim makefiles
alonamid Nov 28, 2018
d541ecc
fix typo in cl_firesim.sv
alonamid Nov 28, 2018
5765f2a
remove redundant include for xsim
alonamid Nov 29, 2018
9b83501
select frequency from included header
sagark Nov 29, 2018
b136fb7
missing file copy in encrypt.tcl
sagark Nov 29, 2018
ba51a86
vivado didn't like previous style of macro, had to switch to something
sagark Nov 29, 2018
ef82afc
Merge pull request #13 from firesim/firesim-supernode-integration
alonamid Nov 30, 2018
57139f9
more constraints
sagark Dec 6, 2018
50d4a55
Merge pull request #15 from firesim/more-supernode
sagark Dec 9, 2018
71a3610
Add a wildcard to URAM inference constraint
davidbiancolin Dec 14, 2018
4e7b66d
Merge pull request #16 from firesim/uram-wildcard
davidbiancolin Dec 14, 2018
8408bdc
Merge remote-tracking branch 'upstream/master' into aws-fpga-upstream…
sagark Jan 25, 2019
e55961e
update cl_firesim with changes required by upstream aws-fpga 1.4.6
sagark Jan 25, 2019
5730679
fix xsim
sagark Feb 1, 2019
05a5cd4
Merge pull request #17 from firesim/aws-fpga-upstream-1.4.6
sagark Feb 1, 2019
1b6c0d4
Merge pull request #18 from firesim/dev
sagark Feb 25, 2019
31e0854
Merge remote-tracking branch 'upstream/master' into aws-fpga-upstream…
sagark Apr 16, 2019
8896ea1
update gitignore
sagark Apr 17, 2019
2b59f15
Merge pull request #19 from firesim/aws-fpga-upstream-1.4.8
sagark Apr 19, 2019
e408dc3
Generate PLL IP on every build with a single desired frequency
davidbiancolin Apr 23, 2019
f7915f6
Fix FPGA-Level Simulation (#24)
davidbiancolin Feb 6, 2020
e292b3d
Remove unneeded connections between DRAM and F1Shim
davidbiancolin Apr 7, 2020
65deb47
Merge pull request #25 from firesim/dev
davidbiancolin May 31, 2020
f22f7ca
Promote design partially routed and timing failures to fatal errors
davidbiancolin Jul 13, 2020
d65ee3c
Sort paths by slack; and check hold-timing slack
davidbiancolin Jul 15, 2020
85c04dc
Error out on partially routed clock nets
davidbiancolin Jan 26, 2021
b4544da
Merge pull request #29 from firesim/dev
davidbiancolin Jan 27, 2021
f222c86
Merge pull request #31 from firesim/clock-net-failures
davidbiancolin Jan 27, 2021
e9945da
Add strategy to remove -retime flag from Vivado
jerryz123 Feb 25, 2021
94b6b53
Merge pull request #34 from firesim/no-retiming
jerryz123 Mar 2, 2021
10f1708
Finish adding support for NORETIMING strategy
jerryz123 Mar 12, 2021
008f0bf
Merge pull request #35 from firesim/no-retiming
abejgonzalez Mar 30, 2021
3dabfaa
Merge tag 'v1.4.18' into dev
abejgonzalez Mar 30, 2021
48130d2
Suppress same messages as the dma_dram example
davidbiancolin Apr 7, 2021
86023a3
Report clock utilization
davidbiancolin Apr 9, 2021
1ea0db5
Merge remote-tracking branch 'upstream/master' into aws-1.4.18-bump
davidbiancolin Apr 9, 2021
6cd1a8c
add more reports (#37)
timsnyder-siv May 3, 2021
8490605
Demote Route 35-1 back to CW
davidbiancolin Jun 10, 2021
e2a9752
Merge pull request #32 from firesim/dev
davidbiancolin Jun 14, 2021
96fc945
Workaround clock-partitioning error by disabling phys opt
davidbiancolin Jun 10, 2021
080cdf0
Merge remote-tracking branch 'origin/master' into aws-1.4.18-bump
davidbiancolin Jun 14, 2021
7ed2a98
Re-enable post-placement phys_opt
davidbiancolin Jun 15, 2021
c3c590a
Merge pull request #39 from firesim/vivado-2020-bump2
davidbiancolin Jun 17, 2021
59aecdc
Add dont_touch to all dummy clock loads
davidbiancolin Jun 18, 2021
cb2cc9b
Import basic floorplan from cl_dram_dma
davidbiancolin Jun 22, 2021
3f2cace
Merge pull request #40 from firesim/clock-partitioning
davidbiancolin Jul 21, 2021
e0745fa
Update filenames to reflect new output file strategy.
davidbiancolin Jul 2, 2021
bdb6d56
Merge pull request #42 from firesim/file-emission
davidbiancolin Aug 6, 2021
1b2ec84
Selective instantiate DRAM controllers + CDC + Width apaters
davidbiancolin Jul 16, 2021
930468d
Merge remote-tracking branch 'upstream/master' into HEAD
davidbiancolin Sep 24, 2021
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5 changes: 5 additions & 0 deletions .gitignore
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Expand Up @@ -111,3 +111,8 @@ patches/*
.temp

.python-version

# FireSim specific
awsver.txt

sdk/linux_kernel_drivers/xdma/.libxdma.o.d
8 changes: 8 additions & 0 deletions README.md
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@@ -1,3 +1,11 @@
# AWS FPGA Shell for FireSim

This is a fork of [aws-fpga](https://github.com/aws/aws-fpga) used for FireSim. More information about this repo can be found in the [FireSim Changelog](https://github.com/firesim/firesim/blob/master/CHANGELOG.md).

Below is the standard aws-fpga documentation from upstream.

<span style="display: inline-block;">

# Table of Contents

1. [Overview of AWS EC2 FPGA Development Kit](#overview-of-aws-ec2-fpga-development-kit)
Expand Down
1 change: 1 addition & 0 deletions hdk/cl/developer_designs/.gitignore
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cl_Fire*
7 changes: 7 additions & 0 deletions hdk/cl/developer_designs/cl_firesim/.gitignore
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build/constraints/cl_clocks_aws.xdc
build/reports/
build/scripts/.Xil/
build/scripts/*.vivado.log
build/scripts/hd_visual/
build/scripts/last_log
verif/sim/
1 change: 1 addition & 0 deletions hdk/cl/developer_designs/cl_firesim/build/README.md
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../../../../common/shell_stable/new_cl_template/build/README.md
51 changes: 51 additions & 0 deletions hdk/cl/developer_designs/cl_firesim/build/constraints/cl_pnr_user.xdc
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# This contains the CL specific constraints for Top level PNR

create_pblock pblock_CL_top
add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/gen_ddr_tst[0].*}]
add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/ddr_cores.DDR4_0*}]
add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/ddr_inst[0].*}]
add_cells_to_pblock [get_pblocks pblock_CL_top] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/ddr_stat[0].*}]
resize_pblock [get_pblocks pblock_CL_top] -add {CLOCKREGION_X0Y10:CLOCKREGION_X5Y14}
set_property PARENT pblock_CL [get_pblocks pblock_CL_top]

create_pblock pblock_CL_mid
add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/gen_ddr_tst[1].*}]
add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/ddr_cores.DDR4_1*}]
add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/ddr_inst[1].*}]
add_cells_to_pblock [get_pblocks pblock_CL_mid] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/ddr_stat[1].*}]
#resize_pblock [get_pblocks pblock_CL_mid] -add {CLOCKREGION_X0Y5:CLOCKREGION_X3Y9}
resize_pblock [get_pblocks pblock_CL_mid] -add {SLICE_X88Y300:SLICE_X107Y599}
resize_pblock [get_pblocks pblock_CL_mid] -add {DSP48E2_X11Y120:DSP48E2_X13Y239}
resize_pblock [get_pblocks pblock_CL_mid] -add {LAGUNA_X12Y240:LAGUNA_X15Y479}
resize_pblock [get_pblocks pblock_CL_mid] -add {RAMB18_X7Y120:RAMB18_X7Y239}
resize_pblock [get_pblocks pblock_CL_mid] -add {RAMB36_X7Y60:RAMB36_X7Y119}
resize_pblock [get_pblocks pblock_CL_mid] -add {URAM288_X2Y80:URAM288_X2Y159}
resize_pblock [get_pblocks pblock_CL_mid] -add {CLOCKREGION_X0Y5:CLOCKREGION_X2Y9}
set_property SNAPPING_MODE ON [get_pblocks pblock_CL_mid]
set_property PARENT pblock_CL [get_pblocks pblock_CL_mid]

create_pblock pblock_CL_bot
add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/gen_ddr_tst[2].*}]
add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/ddr_cores.DDR4_2*}]
add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/ddr_inst[2].*}]
add_cells_to_pblock [get_pblocks pblock_CL_bot] [get_cells -quiet -hierarchical -filter {NAME =~ WRAPPER_INST/CL/SH_DDR/ddr_stat[2].*}]
#resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X3Y4}
resize_pblock [get_pblocks pblock_CL_bot] -add {SLICE_X88Y0:SLICE_X107Y299}
resize_pblock [get_pblocks pblock_CL_bot] -add {DSP48E2_X11Y0:DSP48E2_X13Y119}
resize_pblock [get_pblocks pblock_CL_bot] -add {LAGUNA_X12Y0:LAGUNA_X15Y239}
resize_pblock [get_pblocks pblock_CL_bot] -add {RAMB18_X7Y0:RAMB18_X7Y119}
resize_pblock [get_pblocks pblock_CL_bot] -add {RAMB36_X7Y0:RAMB36_X7Y59}
resize_pblock [get_pblocks pblock_CL_bot] -add {URAM288_X2Y0:URAM288_X2Y79}
resize_pblock [get_pblocks pblock_CL_bot] -add {CLOCKREGION_X0Y0:CLOCKREGION_X2Y4}
set_property SNAPPING_MODE ON [get_pblocks pblock_CL_bot]
set_property PARENT pblock_CL [get_pblocks pblock_CL_bot]

# False paths to FireSim reset synchronizers
set_false_path -from [get_clocks clk_main_a0] \
-to [get_cells {WRAPPER_INST/CL/pre_sync_rst_n_extra1_reg* \
WRAPPER_INST/CL/pre_sync_rst_n_firesim_reg* \
WRAPPER_INST/CL/rst_firesim_n_sync_reg* \
WRAPPER_INST/CL/rst_extra1_n_sync_reg* }]


set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets WRAPPER_INST/SH/kernel_clks_i/clkwiz_sys_clk/inst/CLK_CORE_DRP_I/clk_inst/clk_out2]
3 changes: 3 additions & 0 deletions hdk/cl/developer_designs/cl_firesim/build/constraints/cl_synth_user.xdc
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# This contains the CL specific constraints for synthesis at the CL level

set_property RAM_STYLE ULTRA [get_cells -hierarchical -regexp firesim_top.*PCISdat/fq/ram_reg.*]
1 change: 1 addition & 0 deletions hdk/cl/developer_designs/cl_firesim/build/scripts/README
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You must build with strategy TIMING
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../../../../../common/shell_stable/build/scripts/aws_build_dcp_from_cl.sh
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