dual: arm: Add a stubbed DynarecCPU class

external/CMakeLists.txt

@@ -5,5 +5,4 @@ if(DUAL_ENABLE_JIT)
   add_subdirectory(lunatic)
 endif()
 
-
-add_subdirectory(oaknut)
+add_subdirectory(oaknut)

src/dual/CMakeLists.txt

@@ -5,6 +5,7 @@ set(CMAKE_CXX_STANDARD 20)
 set(CMAKE_CXX_STANDARD_REQUIRED ON)
 
 set(SOURCES
+  src/arm/dynarec/dynarec_cpu.cpp
   src/arm/interpreter/tablegen/tablegen.cpp
   src/arm/interpreter/interpreter_cpu.cpp
   src/common/scheduler.cpp
@@ -50,6 +51,7 @@ set(SOURCES
 )
 
 set(HEADERS
+  src/arm/dynarec/dynarec_cpu.hpp
   src/arm/interpreter/handlers/arithmetic.inl
   src/arm/interpreter/handlers/handler16.inl
   src/arm/interpreter/handlers/handler32.inl

src/dual/src/arm/dynarec/dynarec_cpu.cpp

@@ -0,0 +1,93 @@
+
+#include <atom/panic.hpp>
+
+#include "dynarec_cpu.hpp"
+
+namespace dual::arm {
+
+DynarecCPU::DynarecCPU(
+  Memory& memory,
+  Scheduler& scheduler,
+  CycleCounter& cycle_counter,
+  Model model,
+  std::span<const AttachCPn> coprocessors
+) {
+}
+
+void DynarecCPU::Reset() {
+  ATOM_PANIC("unimplemented");
+}
+
+u32  DynarecCPU::GetExceptionBase() const {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::SetExceptionBase(u32 address) {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::InvalidateICache() {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::InvalidateICacheRange(u32 address_lo, u32 address_hi) {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::SetUnalignedDataAccessEnable(bool enable) {
+  ATOM_PANIC("unimplemented");
+}
+
+bool DynarecCPU::GetWaitingForIRQ() const {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::SetWaitingForIRQ(bool value) {
+  ATOM_PANIC("unimplemented");
+}
+
+bool DynarecCPU::GetIRQFlag() const {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::SetIRQFlag(bool value) {
+  ATOM_PANIC("unimplemented");
+}
+
+u32 DynarecCPU::GetGPR(GPR reg) const {
+  ATOM_PANIC("unimplemented");
+}
+
+u32 DynarecCPU::GetGPR(GPR reg, Mode mode) const {
+  ATOM_PANIC("unimplemented");
+}
+
+CPU::PSR DynarecCPU::GetCPSR() const {
+  ATOM_PANIC("unimplemented");
+}
+
+CPU::PSR DynarecCPU::GetSPSR(Mode mode) const {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::SetGPR(GPR reg, u32 value) {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::SetGPR(GPR reg, Mode mode, u32 value) {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::SetCPSR(PSR value) {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::SetSPSR(Mode mode, PSR value) {
+  ATOM_PANIC("unimplemented");
+}
+
+void DynarecCPU::Run(int cycles) {
+  ATOM_PANIC("unimplemented");
+}
+
+} // namespace dual::arm

src/dual/src/arm/dynarec/dynarec_cpu.hpp

@@ -0,0 +1,51 @@
+
+#pragma once
+
+#include <dual/arm/cpu.hpp>
+#include <dual/arm/memory.hpp>
+#include <dual/common/scheduler.hpp>
+#include <dual/common/cycle_counter.hpp>
+#include <span>
+
+namespace dual::arm {
+
+class DynarecCPU final : public CPU {
+  public:
+    DynarecCPU(
+      Memory& memory,
+      Scheduler& scheduler,
+      CycleCounter& cycle_counter,
+      Model model,
+      std::span<const AttachCPn> coprocessors = {}
+    );
+
+    void Reset() override;
+
+    u32  GetExceptionBase() const override;
+    void SetExceptionBase(u32 address) override;
+
+    void InvalidateICache() override;
+    void InvalidateICacheRange(u32 address_lo, u32 address_hi) override;
+
+    void SetUnalignedDataAccessEnable(bool enable) override;
+
+    bool GetWaitingForIRQ() const override;
+    void SetWaitingForIRQ(bool value) override;
+
+    bool GetIRQFlag() const override;
+    void SetIRQFlag(bool value) override;
+
+    u32 GetGPR(GPR reg) const override;
+    u32 GetGPR(GPR reg, Mode mode) const override;
+    PSR GetCPSR() const override;
+    PSR GetSPSR(Mode mode) const override;
+
+    void SetGPR(GPR reg, u32 value) override;
+    void SetGPR(GPR reg, Mode mode, u32 value) override;
+    void SetCPSR(PSR value) override;
+    void SetSPSR(Mode mode, PSR value) override;
+
+    void Run(int cycles) override;
+};
+
+} // namespace dual::arm

src/dual/src/nds/nds.cpp

@@ -7,6 +7,7 @@
 #include <dual/nds/header.hpp>
 #include <dual/nds/backup/eeprom.hpp>
 
+#include "arm/dynarec/dynarec_cpu.hpp"
 #include "arm/interpreter/interpreter_cpu.hpp"
 #ifdef DUAL_ENABLE_JIT
   #include "arm/jit/lunatic_cpu.hpp"
@@ -89,6 +90,9 @@ namespace dual::nds {
       default: ATOM_PANIC("unknown CPU emulator");
     }
 
+    // @todo: integrate the new dynamic recompiler more cleanly
+    m_arm7.cpu = std::make_unique<arm::DynarecCPU>(m_arm7.bus, m_scheduler, m_arm7.cycle_counter, arm::CPU::Model::ARM7);
+
     m_arm9.irq.SetCPU(m_arm9.cpu.get());
     m_arm7.irq.SetCPU(m_arm7.cpu.get());
   }