Update readme

Signed-off-by: Alex Forencich <[email protected]>

README.md

@@ -87,6 +87,12 @@ To facilitate the dual-license model, contributions to the project can only be a
     *  Reset synchronizer
     *  Signal synchronizer
 
+## Example designs
+
+Example designs are provided for several different FPGA boards, showcasing many of the capabilities of this library.  Building the example designs will require the appropriate vendor toolchain and may also require tool and IP licenses.
+
+*  Digilent Arty A7 (Xilinx Artix 7 XC7A35T)
+
 ## Testing
 
 Running the included testbenches requires [cocotb](https://github.com/cocotb/cocotb), [cocotbext-axi](https://github.com/alexforencich/cocotbext-axi), [cocotbext-eth](https://github.com/alexforencich/cocotbext-eth), [cocotbext-uart](https://github.com/alexforencich/cocotbext-uart), [cocotbext-pcie](https://github.com/alexforencich/cocotbext-pcie), and [Verilator](https://www.veripool.org/verilator/).  The testbenches can be run with pytest directly (requires [cocotb-test](https://github.com/themperek/cocotb-test)), pytest via tox, or via cocotb makefiles.