Update readme

Signed-off-by: Alex Forencich <[email protected]>
fpganinja · Feb 23, 2025 · 75a7463 · 75a7463
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diff --git a/README.md b/README.md
@@ -44,14 +44,15 @@ To facilitate the dual-license model, contributions to the project can only be a
     *  10/100/1000 RGMII MAC + FIFO
     *  1G MAC
     *  1G MAC + FIFO
-    *  10G MAC
-    *  10G MAC + FIFO
-    *  10G MAC/PHY
-    *  10G MAC/PHY + FIFO
-    *  10G PHY
+    *  10G/25G MAC
+    *  10G/25G MAC + FIFO
+    *  10G/25G MAC/PHY
+    *  10G/25G MAC/PHY + FIFO
+    *  10G/25G PHY
     *  MII PHY interface
     *  GMII PHY interface
     *  RGMII PHY interface
+    *  10G/25G MAC/PHY/GT wrapper for UltraScale/UltraScale+
 *  General input/output
     *  Switch debouncer
     *  Generic IDDR

diff --git a/example/VCU108/fpga/README.md b/example/VCU108/fpga/README.md
@@ -11,7 +11,7 @@ The design places looped-back MACs on the BASE-T and QSFP28 ports as well as a l
 *  RJ-45 Ethernet port with Marvell 88E1111 PHY
     *  Looped-back MAC via SGMII via Xilinx PCS/PMA core and LVDS IOSERDES
 *  QSFP28
-    *  Looped-back 10G or 25G MACs via GTY transceivers
+    *  Looped-back 10GBASE-R or 25GBASE-R MACs via GTY transceivers
 
 ## Board details