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1. accelerator-interface accelerator-interface Public

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2. ibex ibex Public

   Forked from lowRISC/ibex

   Ibex is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, previously known as zero-riscy.

   SystemVerilog

3. opentitan opentitan Public

   Forked from lowRISC/opentitan

   OpenTitan: Open source silicon root of trust

   SystemVerilog

4. riscv-bitmanip riscv-bitmanip Public

   Forked from riscv/riscv-bitmanip

   Working draft of the proposed RISC-V Bitmanipulation extension

   Assembly

5. cv32e40p cv32e40p Public

   Forked from openhwgroup/cv32e40p

   CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform

   SystemVerilog

6. cva6 cva6 Public

   Forked from openhwgroup/cva6

   The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux

   SystemVerilog