add raw hdl21 pdk structure

sky130/hdl21/scripts/export.py

@@ -0,0 +1,106 @@
+#!/usr/bin/env python3
+#
+# Exports PDK data in Vlsir schema format (protobufs).
+
+# To run this without installation (maybe during development), you need to
+# specify paths to VlsirTools, the Vlsir proto bindings, Hdl21 and the Sky130
+# PDK package (this one):
+#   PYTHONPATH=/path/Hdl21/pdks/Sky130:/path/Hdl21:/path/Vlsir/VlsirTools/:/path/Vlsir/bindings/python/ \
+#   ./export.py --text_format
+
+
+import optparse
+
+import google.protobuf.text_format as text_format
+import hdl21 as h
+import vlsir.circuit_pb2 as vlsir_circuit
+from sky130_hdl21 import pdk_data
+from sky130_hdl21.primitives import prim_dicts
+from tabulate import tabulate
+
+
+def define_options(optparser: optparse.OptionParser):
+    optparser.add_option(
+        "-o",
+        "--output",
+        dest="output",
+        default="sky130.primitives.pb",
+        help="name of proto file to export to",
+    )
+    optparser.add_option(
+        "-t",
+        "--text_format",
+        dest="text_format",
+        action="store_true",
+        default=False,
+        help="also export text format version of protobuf",
+    )
+
+
+def collect_other_primitives(
+    defs: dict[str, h.ExternalModule], modules: [h.ExternalModule]
+):
+    table_rows = []
+    for name, module in prim_dicts.ress.items():
+        table_rows.append([name, module.name])
+        modules.append(module)
+    print(tabulate(table_rows))
+
+
+def process(options: optparse.Values):
+    # The primitives are conveniently listed in sky130_hdl21.prim_dicts. You
+    # could also scrape sky130_hdl21.primitives.__dict__, but don't.
+    ext_modules: [h.ExternalModule] = []
+
+    print("Transistors:")
+    table_rows = []
+    for mos_key, module in prim_dicts.xtors.items():
+        name, mos_type, mos_vth, mos_family = mos_key
+        table_rows.append([name, module.name, mos_type, mos_vth, mos_family])
+        ext_modules.append(module)
+    print(tabulate(table_rows))
+
+    others = {
+        "Resistors": prim_dicts.ress,
+        "Diodes": prim_dicts.diodes,
+        "BJTs": prim_dicts.bjts,
+        "VPPs": prim_dicts.vpps,
+    }
+
+    for name, defs in others.items():
+        print(f"{name}:")
+        collect_other_primitives(defs, ext_modules)
+
+    package_pb = vlsir_circuit.Package()
+    package_pb.domain = pdk_data.PDK_NAME
+
+    for module in ext_modules:
+        module_pb = h.proto.exporting.export_external_module(module)
+        for name, param in module.paramtype.__params__.items():
+            param_pb = module_pb.parameters.add()
+            param_pb.name = name
+            param_pb.value.CopyFrom(h.proto.exporting.export_param_value(param.default))
+            param_pb.desc = param.desc
+
+        package_pb.ext_modules.append(module_pb)
+
+    print(f"\nwriting {options.output}")
+    with open(f"{options.output}", "wb") as f:
+        f.write(package_pb.SerializeToString())
+
+    if options.text_format:
+        filename = f"{options.output}.txt"
+        print(f"writing {filename}")
+        with open(filename, "w") as f:
+            f.write(text_format.MessageToString(package_pb))
+
+
+def main():
+    optparser = optparse.OptionParser()
+    define_options(optparser)
+    options, _ = optparser.parse_args()
+    process(options)
+
+
+if __name__ == "__main__":
+    main()

sky130/hdl21/scripts/parse_digital_cells.py

@@ -0,0 +1,37 @@
+def parse_spice_file(file_path, library):
+    logic_modules = []
+
+    acronym = "".join([l[0] for l in library.split()])
+
+    logic_modules.append(acronym + " : Dict[str : h.ExternalModule] = {")
+
+    with open(file_path) as f:
+        for line in f:
+            if line.startswith(".subckt"):
+                # Remove '.subckt' and split the line into words
+                elements = line[7:].split()
+
+                modname = elements[0]
+                # Get the port list
+                ports = elements[1:]
+
+                # Create the logic module string
+                logic_module = (
+                    f'\t "{modname}" : logic_module("{modname}","{library}",{ports}),'
+                )
+                logic_modules.append(logic_module)
+
+    logic_modules.append("}")
+
+    return logic_modules
+
+
+def write_parser_file(logic_modules, output_file):
+    with open(output_file, "w") as f:
+        for module in logic_modules:
+            f.write(module + "\n")
+
+
+# Example usage:
+modules = parse_spice_file("sky130_fd_sc_ls.spice", "Low Speed")
+write_parser_file(modules, "fd_sc_ls.py")

sky130/hdl21/sky130_gf/__init__.py

@@ -0,0 +1,13 @@
+
+from hdl21.pdk import register
+
+# Grab our primary PDK-definition module
+from . import pdk_logic
+from .pdk_logic import *
+
+# The optional external-data installation.
+# Set by an instantiator of `Install`, if available.
+install: Install | None = None
+
+# And register as a PDK module
+register(pdk_logic)