updated riscv-rt crate and handlers

code/uncore/Cargo.toml

@@ -63,7 +63,7 @@ workspace = true
 [dependencies]
 linked_list_allocator = "0.10.5"
 log = "0.4.20"
-riscv-rt = { git = "https://github.com/rust-embedded/riscv-rt.git", rev = "28b916d", features = ["s-mode"] }
+riscv-rt = { version = "0.12.0", features = ["s-mode"] }
 owo-colors = "4.0.0"
 sbi = "0.2.0"
 spin = "0.9.8"

code/uncore/src/library/arch/risc_v/interrupts_exceptions.rs

@@ -0,0 +1,15 @@
+// SPDX-License-Identifier: GPL-3.0-or-later
+
+//! Contains all interrupt handlers. These handlers are set up by [`riscv-rt`].
+
+/// This function is used by [`riscv-rt`] to provide an exception handler.
+#[export_name = "ExceptionHandler"]
+fn default_exception_handler(_trap_frame: &riscv_rt::TrapFrame) -> ! {
+  todo!("Exception occurred but handler has not been written");
+}
+
+/// This function is used by [`riscv-rt`] to provide an interrupt handler.
+#[export_name = "DefaultHandler"]
+fn default_interrupt_handler(_trap_frame: &riscv_rt::TrapFrame) -> ! {
+  todo!("Exception occurred but handler has not been written");
+}

code/uncore/src/library/arch/risc_v/linking.ld

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-3.0-or-later */
 
 /* This script needs to be synchronized with                                 */
-/* https://github.com/rust-embedded/riscv-rt/blob/28b916dc400caef2b3bfd4c5e66130a162e21f26/link-rv64.x */
+/* https://github.com/rust-embedded/riscv/blob/master/riscv-rt/link.x.in     */
 /* and updates to the riscv-rt crate need to be synchronized with            */
 /* the updates the script gets on GitHub.                                    */
 
@@ -48,6 +48,29 @@ REGION_ALIAS(REGION_STACK,  REGION_DRAM);
 PROVIDE(_max_hart_id = 0);
 PROVIDE(_hart_stack_size = 2K);
 
+/* Provide default handlers for possible interrupts and exceptions .         */
+PROVIDE(InstructionMisaligned = ExceptionHandler);
+PROVIDE(InstructionFault = ExceptionHandler);
+PROVIDE(IllegalInstruction = ExceptionHandler);
+PROVIDE(Breakpoint = ExceptionHandler);
+PROVIDE(LoadMisaligned = ExceptionHandler);
+PROVIDE(LoadFault = ExceptionHandler);
+PROVIDE(StoreMisaligned = ExceptionHandler);
+PROVIDE(StoreFault = ExceptionHandler);;
+PROVIDE(UserEnvCall = ExceptionHandler);
+PROVIDE(SupervisorEnvCall = ExceptionHandler);
+PROVIDE(MachineEnvCall = ExceptionHandler);
+PROVIDE(InstructionPageFault = ExceptionHandler);
+PROVIDE(LoadPageFault = ExceptionHandler);
+PROVIDE(StorePageFault = ExceptionHandler);
+
+PROVIDE(SupervisorSoft = DefaultHandler);
+PROVIDE(MachineSoft = DefaultHandler);
+PROVIDE(SupervisorTimer = DefaultHandler);
+PROVIDE(MachineTimer = DefaultHandler);
+PROVIDE(SupervisorExternal = DefaultHandler);
+PROVIDE(MachineExternal = DefaultHandler);
+
 /* Pre-initialization function. If the user overrides this using the         */
 /* `#[pre_init]` attribute or by creating a `__pre_init` function, then the  */
 /* function this points to will be called before the RAM is initialized.     */

code/uncore/src/library/arch/risc_v/mod.rs

@@ -8,7 +8,7 @@
 
 pub mod drivers;
 pub mod heap;
-mod interrupts;
+mod interrupts_exceptions;
 
 /// Architecture-specific functionality before the kernel setup in [`crate::setup_kernel`]
 /// should run.