Add Skinny

Skinny/Skinny_ASIC_1bit_BitSlidingSbox_20190627/RTL/AddConstKey.vhd

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+----------------------------------------------------------------------------------
+-- Copyright 2016-2019:
+--     Amir Moradi & Pascal Sasdrich for the SKINNY Team
+--     https://sites.google.com/site/skinnycipher/
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License as
+-- published by the Free Software Foundation; either version 2 of the
+-- License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- General Public License for more details.
+----------------------------------------------------------------------------------
+
+
+
+-- IMPORTS
+----------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+USE WORK.SKINNYPKG.ALL;
+
+
+
+-- ENTITY
+----------------------------------------------------------------------------------
+ENTITY AddConstKey IS
+	GENERIC ( BS : BLOCK_SIZE 		 := BLOCK_SIZE_64;
+			 	 TS : TWEAK_SIZE 		 := TWEAK_SIZE_1N);
+	PORT ( -- KEY PORT -------------------------------------
+			 ROUND_KEY		: IN	STD_LOGIC_VECTOR((GET_TWEAK_FACT(TS) - 1) DOWNTO 0);
+			 -- CONST PORT -----------------------------------
+			 ROUND_CST		: IN	STD_LOGIC;
+			 -- DATA PORTS -----------------------------------
+			 DATA_IN			: IN	STD_LOGIC;
+			 DATA_OUT		: OUT STD_LOGIC);
+END AddConstKey;
+
+
+
+-- ARCHITECTURE : BIT
+----------------------------------------------------------------------------------
+ARCHITECTURE Bit OF AddConstKey IS
+
+	-- SIGNALS --------------------------------------------------------------------
+	SIGNAL CONST_ADDITION	: STD_LOGIC;
+
+BEGIN
+
+	-- CONSTANT ADDITION ----------------------------------------------------------
+	CONST_ADDITION <= DATA_IN XOR ROUND_CST;
+	-------------------------------------------------------------------------------
+
+	-- ROUNDKEY ADDITION ----------------------------------------------------------
+	T1N : IF TS = TWEAK_SIZE_1N GENERATE
+		DATA_OUT <= CONST_ADDITION XOR ROUND_KEY(0);
+	END GENERATE;
+
+	T2N : IF TS = TWEAK_SIZE_2N GENERATE
+		DATA_OUT <= CONST_ADDITION XOR ROUND_KEY(0) XOR ROUND_KEY(1);
+	END GENERATE;
+
+	T3N : IF TS = TWEAK_SIZE_3N GENERATE
+		DATA_OUT <= CONST_ADDITION XOR ROUND_KEY(0) XOR ROUND_KEY(1) XOR ROUND_KEY(2);
+	END GENERATE;
+	-------------------------------------------------------------------------------
+
+END Bit;

Skinny/Skinny_ASIC_1bit_BitSlidingSbox_20190627/RTL/CellDO.vhd

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+----------------------------------------------------------------------------------
+-- Copyright 2016-2019:
+--     Amir Moradi & Pascal Sasdrich for the SKINNY Team
+--     https://sites.google.com/site/skinnycipher/
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License as
+-- published by the Free Software Foundation; either version 2 of the
+-- License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- General Public License for more details.
+----------------------------------------------------------------------------------
+
+
+
+-- IMPORTS
+----------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+
+
+-- ENTITY
+----------------------------------------------------------------------------------
+ENTITY CellDO IS
+	GENERIC (SIZE : INTEGER);
+   PORT ( CLK	: IN 	STD_LOGIC;
+          D  	: IN 	STD_LOGIC;
+          Q 	: OUT STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0));
+END CellDO;
+
+
+
+-- ARCHITECTURE : STRUCTURAL
+----------------------------------------------------------------------------------
+ARCHITECTURE Structural OF CellDO IS
+
+	-- SIGNALS --------------------------------------------------------------------
+	SIGNAL STATE : STD_LOGIC_VECTOR(SIZE DOWNTO 0);
+
+BEGIN
+
+	STATE(0) <= D;
+
+   DFF : ENTITY work.DataFF GENERIC MAP (SIZE => SIZE) PORT MAP (CLK, STATE((SIZE - 1) DOWNTO 0), STATE(SIZE DOWNTO 1));
+
+	Q <= STATE(SIZE DOWNTO 1);
+
+END Structural;

Skinny/Skinny_ASIC_1bit_BitSlidingSbox_20190627/RTL/CellSB.vhd

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+----------------------------------------------------------------------------------
+-- Copyright 2016-2019:
+--     Amir Moradi & Pascal Sasdrich for the SKINNY Team
+--     https://sites.google.com/site/skinnycipher/
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License as
+-- published by the Free Software Foundation; either version 2 of the
+-- License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- General Public License for more details.
+----------------------------------------------------------------------------------
+
+
+
+-- IMPORTS
+----------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+USE WORK.SKINNYPKG.ALL;
+
+
+
+-- ENTITY
+----------------------------------------------------------------------------------
+ENTITY CellSB IS
+	GENERIC (BS : BLOCK_SIZE);
+   PORT ( CLK	: IN 	STD_LOGIC;
+          SE 	: IN 	STD_LOGIC;
+			 SB	: IN 	STD_LOGIC;
+          D  	: IN 	STD_LOGIC;
+          DS	: IN 	STD_LOGIC;
+          Q 	: OUT STD_LOGIC_VECTOR((GET_WORD_SIZE(BS) - 1) DOWNTO 0));
+END CellSB;
+
+
+
+-- ARCHITECTURE : STRUCTURAL
+----------------------------------------------------------------------------------
+ARCHITECTURE Structural OF CellSB IS
+
+	-- COMPONENTS -----------------------------------------------------------------
+	COMPONENT dflipfloplw IS
+	PORT ( CLK  : IN  STD_LOGIC;
+			 SEL	: IN  STD_LOGIC;
+			 D0   : IN  STD_LOGIC;
+			 D1   : IN  STD_LOGIC;
+			 Q    : OUT STD_LOGIC);
+	END COMPONENT;
+
+	-- CONSTANTS ------------------------------------------------------------------
+	CONSTANT W : INTEGER := GET_WORD_SIZE(BS);
+
+	-- SIGNALS --------------------------------------------------------------------
+	SIGNAL STATE, SBOX_IN, SBOX_OUT : STD_LOGIC_VECTOR((W - 1) DOWNTO 0);
+
+BEGIN
+
+	-- SIGNAL ASSIGNMENTS ---------------------------------------------------------
+	SBOX_IN 	<= STATE((W - 1) DOWNTO 0);
+	Q((W - 2) DOWNTO 0) <= STATE((W - 2) DOWNTO 0);
+
+ 	-- MULTIPLEXERS ---------------------------------------------------------------
+	Q(W - 1) <= SBOX_OUT(W - 1) WHEN (SB = '1') ELSE STATE(W - 1);
+
+	-- SUBSTITUTION ---------------------------------------------------------------
+	S : ENTITY work.SBox GENERIC MAP (BS => BS) PORT MAP (SBOX_IN, SBOX_OUT);
+
+	-- REGISTER STAGE -------------------------------------------------------------
+   SF0 : dflipfloplw PORT MAP (CLK, SE, D, DS, STATE(0));
+   SFF : ENTITY work.ScanFF GENERIC MAP (SIZE => (W - 1)) PORT MAP (CLK, SB, STATE((W - 2) DOWNTO 0), SBOX_OUT((W - 2) DOWNTO 0), STATE((W - 1) DOWNTO 1));
+
+
+END Structural;

Skinny/Skinny_ASIC_1bit_BitSlidingSbox_20190627/RTL/CellSD.vhd

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+----------------------------------------------------------------------------------
+-- Copyright 2016-2019:
+--     Amir Moradi & Pascal Sasdrich for the SKINNY Team
+--     https://sites.google.com/site/skinnycipher/
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License as
+-- published by the Free Software Foundation; either version 2 of the
+-- License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- General Public License for more details.
+----------------------------------------------------------------------------------
+
+
+
+-- IMPORTS
+----------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+
+
+-- ENTITY
+----------------------------------------------------------------------------------
+ENTITY CellSD IS
+	GENERIC (SIZE : INTEGER);
+   PORT ( CLK	: IN 	STD_LOGIC;
+          SE 	: IN 	STD_LOGIC;
+          D  	: IN 	STD_LOGIC;
+          DS	: IN 	STD_LOGIC;
+          Q 	: OUT STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0));
+END CellSD;
+
+
+
+-- ARCHITECTURE : STRUCTURAL
+----------------------------------------------------------------------------------
+ARCHITECTURE Structural OF CellSD IS
+
+	-- COMPONENTS -----------------------------------------------------------------
+	COMPONENT dflipfloplw IS
+	PORT ( CLK  : IN  STD_LOGIC;
+			 SEL	: IN  STD_LOGIC;
+			 D0   : IN  STD_LOGIC;
+			 D1   : IN  STD_LOGIC;
+			 Q    : OUT STD_LOGIC);
+	END COMPONENT;
+
+	-- SIGNALS --------------------------------------------------------------------
+	SIGNAL STATE : STD_LOGIC_VECTOR((SIZE - 1) DOWNTO 0);
+
+BEGIN
+
+   SFF : dflipfloplw PORT MAP (CLK, SE, D, DS, STATE(0));
+
+   DFF : ENTITY work.DataFF GENERIC MAP (SIZE => (SIZE - 1)) PORT MAP (CLK, STATE((SIZE - 2) DOWNTO 0), STATE((SIZE - 1) DOWNTO 1));
+
+	Q <= STATE;
+
+END Structural;

Skinny/Skinny_ASIC_1bit_BitSlidingSbox_20190627/RTL/CellT2.vhd

@@ -0,0 +1,68 @@
+----------------------------------------------------------------------------------
+-- Copyright 2016-2019:
+--     Amir Moradi & Pascal Sasdrich for the SKINNY Team
+--     https://sites.google.com/site/skinnycipher/
+--
+-- This program is free software; you can redistribute it and/or
+-- modify it under the terms of the GNU General Public License as
+-- published by the Free Software Foundation; either version 2 of the
+-- License, or (at your option) any later version.
+--
+-- This program is distributed in the hope that it will be useful, but
+-- WITHOUT ANY WARRANTY; without even the implied warranty of
+-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
+-- General Public License for more details.
+----------------------------------------------------------------------------------
+
+
+
+-- IMPORTS
+----------------------------------------------------------------------------------
+LIBRARY IEEE;
+USE IEEE.STD_LOGIC_1164.ALL;
+
+USE WORK.SKINNYPKG.ALL;
+
+
+
+-- ENTITY
+----------------------------------------------------------------------------------
+ENTITY CellT2 IS
+	GENERIC (BS : BLOCK_SIZE);
+   PORT ( CLK	: IN 	STD_LOGIC;
+          SE 	: IN 	STD_LOGIC;
+			 SR	: IN 	STD_LOGIC;
+          D  	: IN 	STD_LOGIC;
+          DS	: IN 	STD_LOGIC;
+          Q 	: OUT STD_LOGIC_VECTOR((GET_WORD_SIZE(BS) - 1) DOWNTO 0));
+END CellT2;
+
+
+
+-- ARCHITECTURE : STRUCTURAL
+----------------------------------------------------------------------------------
+ARCHITECTURE Structural OF CellT2 IS
+
+	-- CONSTANTS ------------------------------------------------------------------
+	CONSTANT W : INTEGER := GET_WORD_SIZE(BS);
+
+	-- SIGNALS --------------------------------------------------------------------
+	SIGNAL LFSR  : STD_LOGIC_VECTOR((W - 1) DOWNTO 0);
+	SIGNAL STATE : STD_LOGIC_VECTOR( 	 W  DOWNTO 0);
+
+BEGIN
+
+	-- SIGNAL ASSIGNMENTS ---------------------------------------------------------
+	Q <= STATE(W DOWNTO 1);
+
+	-- MULTIPLEXERS ---------------------------------------------------------------
+	STATE(0) <= DS WHEN (SE = '1') ELSE D;
+
+	-- LFSR -----------------------------------------------------------------------
+	LFSR <= STATE((W - 2) DOWNTO 0) & (STATE(W - 1) XOR STATE(W - (W / 8) - 2));
+
+	-- REGISTER STAGE -------------------------------------------------------------
+   SFF : ENTITY work.ScanFF GENERIC MAP (SIZE => W) PORT MAP (CLK, SR, STATE((W - 1) DOWNTO 0), LFSR((W - 1) DOWNTO 0), STATE(W DOWNTO 1));
+
+
+END Structural;