update aes and prince

hadipourh · Nov 29, 2021 · 96cdd15 · 96cdd15
1 parent 7fcbee4
commit 96cdd15
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Showing 2 changed files with 2 additions and 2 deletions.
diff --git a/AES-VHDL b/AES-VHDL
diff --git a/prince-vhdl b/prince-vhdl
+95 −0		sim/prince_axis_tb.v
+71 −0		sim/prince_tb.v
+2 −0		sim/prince_tb_features.v
+111 −0		verilog/axi_stream_wrapper.v
+34 −0		verilog/linear_m.v
+30 −0		verilog/linear_m_inv.v
+76 −0		verilog/linear_mprime.v
+190 −0		verilog/prince_core.v
+61 −0		verilog/prince_top.v
+64 −0		verilog/sbox.v
+64 −0		verilog/sbox_inv.v