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Some misc fixes #2607

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merged 4 commits into from
Apr 25, 2024
Merged

Some misc fixes #2607

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5f473d5
Fix IAR breakpoint test.
HiFiPhile Apr 18, 2024
13bde7a
uac2: return on clear_feature.
HiFiPhile Apr 23, 2024
f32eb07
stm32u5: fix IAR build.
HiFiPhile Apr 23, 2024
c2f8362
Disable EPs correctly to clear incomplete transfer.
HiFiPhile Apr 23, 2024
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2 changes: 1 addition & 1 deletion hw/bsp/stm32u5/family.c
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Original file line number Diff line number Diff line change
Expand Up @@ -249,7 +249,7 @@ uint32_t board_millis(void) {
#endif

void HardFault_Handler(void) {
asm("bkpt");
asm("bkpt 1");
}

// Required by __libc_init_array in startup code if we are compiling using
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5 changes: 4 additions & 1 deletion src/class/audio/audio_device.c
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Expand Up @@ -2015,7 +2015,10 @@ static bool audiod_control_request(uint8_t rhport, tusb_control_request_t const
case TUSB_REQ_SET_INTERFACE:
return audiod_set_interface(rhport, p_request);

// Unknown/Unsupported request
case TUSB_REQ_CLEAR_FEATURE:
return true;

// Unknown/Unsupported request
default: TU_BREAKPOINT(); return false;
}
}
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3 changes: 2 additions & 1 deletion src/common/tusb_verify.h
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Expand Up @@ -76,7 +76,8 @@
#endif

// Halt CPU (breakpoint) when hitting error, only apply for Cortex M3, M4, M7, M33. M55
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__)
#if defined(__ARM_ARCH_7M__) || defined (__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) || \
defined(__ARM7M__) || defined (__ARM7EM__) || defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__)
#define TU_BREAKPOINT() do \
{ \
volatile uint32_t* ARM_CM_DHCSR = ((volatile uint32_t*) 0xE000EDF0UL); /* Cortex M CoreDebug->DHCSR */ \
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21 changes: 16 additions & 5 deletions src/portable/synopsys/dwc2/dcd_dwc2.c
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Expand Up @@ -202,10 +202,10 @@ static void edpt_activate(uint8_t rhport, tusb_desc_endpoint_t const * p_endpoin
(xfer->max_size << DOEPCTL_MPSIZ_Pos);

if (dir == TUSB_DIR_OUT) {
dwc2->epout[epnum].doepctl |= dxepctl;
dwc2->epout[epnum].doepctl = dxepctl;
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@HiFiPhile HiFiPhile Apr 23, 2024 •
edited
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dxepctl is not cleared on bus reset, besides no need to do masked write.

dwc2->daintmsk |= TU_BIT(DAINTMSK_OEPM_Pos + epnum);
} else {
dwc2->epin[epnum].diepctl |= dxepctl | (epnum << DIEPCTL_TXFNUM_Pos);
dwc2->epin[epnum].diepctl = dxepctl | (epnum << DIEPCTL_TXFNUM_Pos);
dwc2->daintmsk |= (1 << (DAINTMSK_IEPM_Pos + epnum));
}
}
Expand Down Expand Up @@ -280,10 +280,17 @@ static void bus_reset(uint8_t rhport) {
dwc2->epout[n].doepctl |= DOEPCTL_SNAK;
}

// 2. Disable all IN endpoints
for (uint8_t n = 0; n < ep_count; n++) {
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@HiFiPhile HiFiPhile Apr 23, 2024 •
edited
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If there are pending IN transfer on bus reset, eg. in cdc echo test do only write without read:
Since EPENA is not cleared on reset, once the EP is opened it will enter DIEPINT_TXFE interrupt and try to write packet and cause access violation.

if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
}
}

fifo_flush_tx(dwc2, 0x10); // all tx fifo
fifo_flush_rx(dwc2);

// 2. Set up interrupt mask
// 3. Set up interrupt mask
dwc2->daintmsk = TU_BIT(DAINTMSK_OEPM_Pos) | TU_BIT(DAINTMSK_IEPM_Pos);
dwc2->doepmsk = DOEPMSK_STUPM | DOEPMSK_XFRCM;
dwc2->diepmsk = DIEPMSK_TOM | DIEPMSK_XFRCM;
Expand Down Expand Up @@ -704,11 +711,15 @@ void dcd_edpt_close_all(uint8_t rhport) {

for (uint8_t n = 1; n < ep_count; n++) {
// disable OUT endpoint
dwc2->epout[n].doepctl = 0;
if (dwc2->epout[n].doepctl & DOEPCTL_EPENA) {
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Write dxepctl to 0 won't clear EPENA.

dwc2->epout[n].doepctl |= DOEPCTL_SNAK | DOEPCTL_EPDIS;
}
xfer_status[n][TUSB_DIR_OUT].max_size = 0;

// disable IN endpoint
dwc2->epin[n].diepctl = 0;
if (dwc2->epin[n].diepctl & DIEPCTL_EPENA) {
dwc2->epin[n].diepctl |= DIEPCTL_SNAK | DIEPCTL_EPDIS;
}
xfer_status[n][TUSB_DIR_IN].max_size = 0;
}

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