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Update README.md
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Add GPIO interrupt table
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Hex-Five-Labs authored Jan 23, 2024
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# X300

This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its [MultiZone Security Trusted Execution Environment](https://github.com/hex-five/multizone-sdk) and [MultiZone Security Trusted Firmware](https://github.com/hex-five/multizone-iot-sdk). The X300 is an enhanced secure version of the - now archived - [SiFive's Freedom E300 Platform](https://github.com/sifive/freedom) built around the RISC-V Rocket chip originally developed at U.C. Berkeley.
This repository contains the hardware design source files of the Hex Five X300 RISC-V SoC. The X300 SoC is Hex Five's official reference platform for its [MultiZone Security Trusted Execution Environment](https://github.com/hex-five/multizone-sdk) and [MultiZone Security Trusted Firmware](https://github.com/hex-five/multizone-iot-sdk). The X300 is an enhanced secure version of the [SiFive's Freedom E300 Platform](https://github.com/sifive/freedom) built around the RISC-V Rocket chip originally developed at U.C. Berkeley.

Feature comparison between E300 (not secure) and X300 (secure):

Expand All @@ -21,7 +21,7 @@ Like the Freedom E300 Arty FPGA Dev Kit, the X300 is designed to work with the [

### Bootrom & Trusted Firmware

The default bootrom consists of a program that immediately jumps to address 0x20400000, which is 0x400000 bytes into the SPI flash memory on the Arty board. The default bitstream files include no other firmware. A fully functional state-of-the-art trusted firmware stack for this device is available at https://github.com/hex-five/multizone-iot-sdk and included pre-built in the alternative bitstreams [multizone-iot-sdk-arty-35t.mcs](https://github.com/hex-five/multizone-fpga/releases/download/v2.0.0/multizone-iot-sdk-arty-35t.mcs) and [multizone-iot-sdk-arty-100t.mcs](https://github.com/hex-five/multizone-fpga/releases/download/v2.0.0/multizone-iot-sdk-arty-100t.mcs).
The default bootrom consists of a program that immediately jumps to address 0x20400000, which is 0x400000 bytes into the SPI flash memory on the Arty board. The default bitstream files include no other firmware. A fully functional state-of-the-art trusted firmware stack for this device is available at https://github.com/hex-five/multizone-iot-sdk including pre-built bitstreams for ARTY 35T and ARTY 100T.

### Quick Start

Expand All @@ -30,7 +30,7 @@ Prebuilt bitstream files are provided as release assets ready to download and pr
- [X300ArtyA7-35T.mcs](https://github.com/hex-five/multizone-fpga/releases/download/v2.0.0/X300ArtyA7-35T.mcs)
- [X300ArtyA7-100T.mcs](https://github.com/hex-five/multizone-fpga/releases/download/v2.0.0/X300ArtyA7-100T.mcs)

If you don't need to modify the hardware design, you can skip the next sections and jump directly to the [Program](#program) section.
If you don't intend to modify the design of the hardware, you can skip the next sections and jump directly to the [Program](#program) section.

## Requirements

Expand Down Expand Up @@ -92,3 +92,39 @@ To program the SPI flash with Vivado:
- Select OK
- Once the programming completes in Vivado, press the “PROG” Button on the Arty board to
load the image into the FPGA

## Appendix - GPIO interrupts table
| GPIO | ARTY CONNECTION | CLINT IRQ | PLIC IRQ |
| -----| ----------------| --------- | -------- |
| 0 | IO8 | | 22 |
| 1 | | | |
| 2 | | | |
| 3 | | | |
| 4 | IO12 | | 26 |
| 5 | IO13 | | 27 |
| 6 | | | |
| 7 | | | |
| 8 | PMODA [1] | | 30 |
| 9 | PMODA [2] | | 31 |
| 10 | PMODA [3] | | 32 |
| 11 | PMODA [4] | | 33 |
| 12 | | | |
| 13 | | | |
| 14 | | | |
| 15 | BTN0 | 16 | 37 |
| 16 | | | |
| 17 | | | |
| 18 | IO02 | | 40 |
| 19 | | | |
| 20 | IO04 | | 42 |
| 21 | | | |
| 22 | | | |
| 23 | IO07 | | 45 |
| 24 | | | |
| 25 | | | |
| 26 | | | |
| 27 | | | |
| 28 | | | |
| 29 | | | |
| 30 | BTN1 | 17 | 52 |
| 31 | BTN2 | 18 | 53 |

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