Developer release v0.9.5

tenyr v0.9.5 is a general developer release. Notable changes since v0.9.4 include :

• adding a ~/.tsimrc file (à la --options=file) that is loaded by a new default recipe
• running recipes in the order they are specified, instead of reverse order
• allowing simulations to continue in the face of device errors
• restoring serial input functionality in a limited way
• adding a new BRAM-optimized 10x15 font and associated build tools
• changing VGA output to be 64x32 text columns (down from 80x40)
• replacing third-party VHDL VGA IP with scratch-written Verilog module
• correcting reported column numbers for syntax errors
• adding @+var and @=var shorthand forms
• expanding op tests to test op types 0, 1, and 2

The new font was designed to be compressed into an 18kbit block RAM by minimizing the number of unique pixel rows in the font. This compression has not yet been done, but has been proven possible.