πΌ Iβm currently ASIC Digital Design Engineer at Monolithic Power Systems (MPS)
π Graduated as Ph.D. in Computer Engineering
Spanish and Chinese as native speaker
π
Working from home
Digital Design Engineer, Ph.D.
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Monolithic Power Systems (MPS)
- Barcelona, Spain
- https://scholar.google.es/citations?user=R2ofGc8AAAAJ&hl=es
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UNSAMDCI/PDK_ONC5
UNSAMDCI/PDK_ONC5 PublicEducational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
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axi_uartlite_pynq
axi_uartlite_pynq PublicForked from parthpower/axi_uartlite_pynq
PYNQ-Z1/Z2 Compatible Python helper functions for AXI UARTLITE IP Core of Xilinx
Tcl 1
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nb-ldpc-riscv
nb-ldpc-riscv PublicIntegration of a Real-Time CCSDS 410.0-B-32 Error-Correction Decoder on FPGA-Based RISC-V SoCs Using RISC-V Vector Extension
C 4
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