Skip to content
View lidapang's full-sized avatar
  • Cadence
  • shanghai

Block or report lidapang

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse

Popular repositories Loading

  1. BuyHouse BuyHouse Public

    买房前最好看一下

    8 2

  2. zfft zfft Public

    zoom FFT in python

    Python 5 1

  3. rsa rsa Public

    RSA cryptosystem implementation in Verilog

    Verilog 2

  4. Stream-multiprocessor-design Stream-multiprocessor-design Public

    Forked from xihuai18/Stream-multiprocessor-design

    Verilog 2

  5. riscv-vip riscv-vip Public

    Forked from jerralph/riscv-vip

    For pre-silicon developers of RISC-V systems, riscv-vip is a SystemVerilog project that helps with pre-si verification and debug

    SystemVerilog 2 1

  6. books books Public

    Forked from programthink/books

    【编程随想】收藏的电子书清单(多个学科,含下载链接)

    2

6 contributions in the last year

Contribution Graph
Day of Week March April May June July August September October November December January February
Sunday
Monday
Tuesday
Wednesday
Thursday
Friday
Saturday
Less
No contributions.
Low contributions.
Medium-low contributions.
Medium-high contributions.
High contributions.
More

Contribution activity

March 2025

lidapang has no activity yet for this period.
Loading

Seeing something unexpected? Take a look at the GitHub profile guide.