Skip to content

Commit

Permalink
Bump version: 0.7.0 → 0.7.1
Browse files Browse the repository at this point in the history
  • Loading branch information
liweiwei committed Aug 11, 2021
1 parent a13aacf commit e2e14a0
Show file tree
Hide file tree
Showing 3 changed files with 4 additions and 3 deletions.
2 changes: 1 addition & 1 deletion riscv_isac/__init__.py
Original file line number Diff line number Diff line change
Expand Up @@ -4,4 +4,4 @@

__author__ = """InCore Semiconductors Pvt Ltd"""
__email__ = '[email protected]'
__version__ = '0.7.0'
__version__ = '0.7.1'
3 changes: 2 additions & 1 deletion setup.cfg
Original file line number Diff line number Diff line change
@@ -1,5 +1,5 @@
[bumpversion]
current_version = 0.7.0
current_version = 0.7.1
commit = True
tag = True

Expand All @@ -18,3 +18,4 @@ universal = 1
exclude = docs

[aliases]

2 changes: 1 addition & 1 deletion setup.py
Original file line number Diff line number Diff line change
Expand Up @@ -26,7 +26,7 @@ def read_requires():

setup(
name='riscv_isac',
version='0.7.0',
version='0.7.1',
description="RISC-V ISAC",
long_description=readme + '\n\n',
classifiers=[
Expand Down

0 comments on commit e2e14a0

Please sign in to comment.