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680 Open 1,414 Closed
680 Open 1,414 Closed
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Issues list

[FIRRTL] Parser Accepts Duplicated Names Under Layerblock bug Something isn't working FIRRTL Involving the `firrtl` dialect good first issue Good for newcomers
#7773 opened Nov 5, 2024 by seldridge
1
[Calyx] Copy attributes when creating new top level function
#7764 opened Nov 2, 2024 by jiahanxie353
@jiahanxie353
[circt-verilog] zero parameter at module declaration fails when used Moore
#7753 opened Oct 31, 2024 by dacsson
2
[Comb] i0 in concat is not folded
#7726 opened Oct 23, 2024 by uenoku
[LowerToHW] Failure when lowering bundle_create which contains zero bit
#7721 opened Oct 22, 2024 by uenoku
[ESI][Runtime][Cosim] Terminate with "pure virtual called" ESI
#7713 opened Oct 17, 2024 by teqdruid
[circt-lec] Report failing points enhancement New feature or request Logical Equivalence
#7711 opened Oct 17, 2024 by uenoku
1
[Verif] Add an optional name attribute to SymbolicValueOp
#7708 opened Oct 15, 2024 by uenoku
[ExportVerilog][COMB] Crash in circt-opt: Variadic Operand Handling in ExportVerilog
#7698 opened Oct 13, 2024 by YangWiz
3
[Sim] Combine integer formatting ops into one op Simulator
#7692 opened Oct 10, 2024 by fabianschuiki
4
[FIRRTL] InferWidths: error can point at operation not involved in constraint bug Something isn't working FIRRTL Involving the `firrtl` dialect
#7689 opened Oct 9, 2024 by youngar
[Calyx] IfOp's group has to be a CombGroupOp? Calyx The Calyx dialect
#7682 opened Oct 8, 2024 by jiahanxie353
3
[FIRRTL] FSRT: not finding all no-reset registers bug Something isn't working FIRRTL Involving the `firrtl` dialect
#7679 opened Oct 8, 2024 by youngar
2
[FIRRTL] FRT: treats different encodings of register resets differently FIRRTL Involving the `firrtl` dialect
#7678 opened Oct 8, 2024 by youngar
3
[FIRRTL] SFCCompat: can select different values for a single invalid value FIRRTL Involving the `firrtl` dialect
#7677 opened Oct 8, 2024 by youngar
6
[FIRRTL] InferResets FullReset (formerly FART) does not add resets to not reset fields of partially reset registers
#7675 opened Oct 8, 2024 by jackkoenig
1
[FIRRTL] FART: Does not process modules not reachable from the main module bug Something isn't working FIRRTL Involving the `firrtl` dialect
#7674 opened Oct 7, 2024 by youngar
[LLHD][ProcessLowering] Incorrectly inlines aliasing drives bug Something isn't working LLHD
#7665 opened Oct 4, 2024 by maerhart
[HWToSMT] Support hw.array_create and hw.array_get
#7664 opened Oct 4, 2024 by uenoku
1
[Verif] Lowering from verif.formal to verif.bmc verif
#7662 opened Oct 4, 2024 by dobios
@TaoBi22
2
[FIRRTL] FIRRTL needs a contract interface FIRRTL Involving the `firrtl` dialect verif
#7661 opened Oct 4, 2024 by dobios
2
[FIRRTL] Layers and Analog FIRRTL Involving the `firrtl` dialect
#7649 opened Sep 30, 2024 by dtzSiFive
[Seq] Move SeqToSV tests from test/Dialect/Seq to test/Conversion/SeqToSV good first issue Good for newcomers Seq Involving the `seq` dialect
#7637 opened Sep 26, 2024 by uenoku
2
[SV] [FIRRTL] Add intrinsics for sampled value functions
#7636 opened Sep 26, 2024 by unlsycn
7
[MooreToCore] Support net op good first issue Good for newcomers Moore
#7629 opened Sep 25, 2024 by fabianschuiki
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