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[GlobalISel][AArch64][AMDGPU] Expand FPOWI into series of multiplicat…
…ion (#95217) SelectionDAG already converts FPOWI into a series of optimized multiplications, this patch introduces the same optimization into GlobalISel.
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26 changes: 26 additions & 0 deletions
26
llvm/test/CodeGen/AArch64/GlobalISel/combine-fpowi-optsize.ll
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | ||
; RUN: llc < %s -mtriple=aarch64-unknown-unknown | FileCheck %s | ||
; RUN: llc < %s -mtriple=aarch64-unknown-unknown -global-isel | FileCheck %s | ||
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define double @pow_optsize(double %x) nounwind optsize { | ||
; CHECK-LABEL: pow_optsize: | ||
; CHECK: // %bb.0: // %entry | ||
; CHECK-NEXT: mov w0, #15 // =0xf | ||
; CHECK-NEXT: b __powidf2 | ||
entry: | ||
%0 = call double @llvm.powi.f64.i32(double %x, i32 15) | ||
ret double %0 | ||
} | ||
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define double @pow_optsize_expand(double %x) nounwind optsize { | ||
; CHECK-LABEL: pow_optsize_expand: | ||
; CHECK: // %bb.0: // %entry | ||
; CHECK-NEXT: fmul d0, d0, d0 | ||
; CHECK-NEXT: fmul d0, d0, d0 | ||
; CHECK-NEXT: fmul d0, d0, d0 | ||
; CHECK-NEXT: fmul d0, d0, d0 | ||
; CHECK-NEXT: ret | ||
entry: | ||
%0 = call double @llvm.powi.f64.i32(double %x, i32 16) | ||
ret double %0 | ||
} |
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py | ||
# RUN: llc -o - -mtriple=aarch64-unknown-unknown -run-pass=aarch64-prelegalizer-combiner -verify-machineinstrs %s | FileCheck %s | ||
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--- | ||
name: fpowi_s64_zero | ||
body: | | ||
bb.0: | ||
liveins: $d0, $w0 | ||
; CHECK-LABEL: name: fpowi_s64_zero | ||
; CHECK: liveins: $d0, $w0 | ||
; CHECK-NEXT: {{ $}} | ||
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00 | ||
; CHECK-NEXT: $d0 = COPY [[C]](s64) | ||
%0:_(s64) = COPY $d0 | ||
%1:_(s32) = COPY $w0 | ||
%2:_(s32) = G_CONSTANT i32 0 | ||
%3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FPOWI %0, %2(s32) | ||
$d0 = COPY %3(s64) | ||
... | ||
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--- | ||
name: fpowi_s32_zero | ||
body: | | ||
bb.0: | ||
liveins: $d0, $w0 | ||
; CHECK-LABEL: name: fpowi_s32_zero | ||
; CHECK: liveins: $d0, $w0 | ||
; CHECK-NEXT: {{ $}} | ||
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 | ||
; CHECK-NEXT: $s0 = COPY [[C]](s32) | ||
%0:_(s32) = COPY $s0 | ||
%1:_(s32) = COPY $w0 | ||
%2:_(s32) = G_CONSTANT i32 0 | ||
%3:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOWI %0, %2(s32) | ||
$s0 = COPY %3(s32) | ||
... | ||
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--- | ||
name: fpowi_positive | ||
body: | | ||
bb.0: | ||
liveins: $d0, $w0 | ||
; CHECK-LABEL: name: fpowi_positive | ||
; CHECK: liveins: $d0, $w0 | ||
; CHECK-NEXT: {{ $}} | ||
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0 | ||
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY]] | ||
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[FMUL]], [[FMUL]] | ||
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[FMUL1]] | ||
; CHECK-NEXT: $d0 = COPY [[FMUL2]](s64) | ||
%0:_(s64) = COPY $d0 | ||
%1:_(s32) = COPY $w0 | ||
%2:_(s32) = G_CONSTANT i32 5 | ||
%3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FPOWI %0, %2(s32) | ||
$d0 = COPY %3(s64) | ||
... | ||
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--- | ||
name: fpowi_s64_negative | ||
body: | | ||
bb.0: | ||
liveins: $d0, $w0 | ||
; CHECK-LABEL: name: fpowi_s64_negative | ||
; CHECK: liveins: $d0, $w0 | ||
; CHECK-NEXT: {{ $}} | ||
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0 | ||
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[COPY]] | ||
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s64) = G_FMUL [[FMUL]], [[FMUL]] | ||
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s64) = G_FMUL [[COPY]], [[FMUL1]] | ||
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 1.000000e+00 | ||
; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FDIV [[C]], [[FMUL2]] | ||
; CHECK-NEXT: $d0 = COPY [[FDIV]](s64) | ||
%0:_(s64) = COPY $d0 | ||
%1:_(s32) = COPY $w0 | ||
%2:_(s32) = G_CONSTANT i32 -5 | ||
%3:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FPOWI %0, %2(s32) | ||
$d0 = COPY %3(s64) | ||
... | ||
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--- | ||
name: fpowi_s32_negative | ||
body: | | ||
bb.0: | ||
liveins: $d0, $w0 | ||
; CHECK-LABEL: name: fpowi_s32_negative | ||
; CHECK: liveins: $d0, $w0 | ||
; CHECK-NEXT: {{ $}} | ||
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $s0 | ||
; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY]] | ||
; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FMUL]], [[FMUL]] | ||
; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[FMUL1]] | ||
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 1.000000e+00 | ||
; CHECK-NEXT: [[FDIV:%[0-9]+]]:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FDIV [[C]], [[FMUL2]] | ||
; CHECK-NEXT: $s0 = COPY [[FDIV]](s32) | ||
%0:_(s32) = COPY $s0 | ||
%1:_(s32) = COPY $w0 | ||
%2:_(s32) = G_CONSTANT i32 -5 | ||
%3:_(s32) = nnan ninf nsz arcp contract afn reassoc G_FPOWI %0, %2(s32) | ||
$s0 = COPY %3(s32) | ||
... | ||
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--- | ||
name: fpowi_libcall | ||
body: | | ||
bb.0: | ||
liveins: $d0, $w0 | ||
; CHECK-LABEL: name: fpowi_libcall | ||
; CHECK: liveins: $d0, $w0 | ||
; CHECK-NEXT: {{ $}} | ||
; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $d0 | ||
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w0 | ||
; CHECK-NEXT: [[FPOWI:%[0-9]+]]:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FPOWI [[COPY]], [[COPY1]](s32) | ||
; CHECK-NEXT: $d0 = COPY [[FPOWI]](s64) | ||
%0:_(s64) = COPY $d0 | ||
%1:_(s32) = COPY $w0 | ||
%2:_(s64) = nnan ninf nsz arcp contract afn reassoc G_FPOWI %0, %1(s32) | ||
$d0 = COPY %2(s64) | ||
... |
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