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[topgen] Generate files for all address spaces #4498

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[topgen] Generate files for all address spaces

[topgen] Generate files for all address spaces #4498

Triggered via pull request January 16, 2025 16:36
@a-willa-will
synchronize #25894
a-will:addr-space-output-redo
Status Cancelled
Total duration 50m 32s
Artifacts 3

ci.yml

on: pull_request
Lint (quick)
3m 46s
Lint (quick)
Earl Grey for CW310 Hyperdebug  /  Build bitstream
0s
Earl Grey for CW310 Hyperdebug / Build bitstream
Earl Grey for CW340  /  Build bitstream
0s
Earl Grey for CW340 / Build bitstream
Earl Grey for CW310  /  Build bitstream
0s
Earl Grey for CW310 / Build bitstream
Lint (slow)
12m 1s
Lint (slow)
Build documentation
5m 28s
Build documentation
Airgapped build
8m 36s
Airgapped build
Verible lint
1m 9s
Verible lint
Run OTBN smoke Test
2m 38s
Run OTBN smoke Test
Run OTBN crypto tests
3m 17s
Run OTBN crypto tests
Verilated English Breakfast
8m 13s
Verilated English Breakfast
Verilated Earl Grey
46m 27s
Verilated Earl Grey
CW305's Bitstream
23m 10s
CW305's Bitstream
Build Docker Containers
2m 59s
Build Docker Containers
Build and test software
2m 38s
Build and test software
CW310 Manufacturing Tests  /  FPGA test
CW310 Manufacturing Tests / FPGA test
CW310 ROM_EXT Tests  /  FPGA test
CW310 ROM_EXT Tests / FPGA test
CW310 SiVal ROM_EXT Tests  /  FPGA test
CW310 SiVal ROM_EXT Tests / FPGA test
CW310 SiVal Tests  /  FPGA test
CW310 SiVal Tests / FPGA test
CW340 Manufacturing Tests  /  FPGA test
CW340 Manufacturing Tests / FPGA test
CW340 ROM Tests  /  FPGA test
CW340 ROM Tests / FPGA test
CW340 ROM_EXT Tests  /  FPGA test
CW340 ROM_EXT Tests / FPGA test
CW340 SiVal ROM_EXT Tests  /  FPGA test
CW340 SiVal ROM_EXT Tests / FPGA test
CW340 SiVal Tests  /  FPGA test
CW340 SiVal Tests / FPGA test
CW340 Test ROM Tests  /  FPGA test
CW340 Test ROM Tests / FPGA test
CW310 ROM Tests  /  FPGA test
CW310 ROM Tests / FPGA test
CW310 Test ROM Tests  /  FPGA test
CW310 Test ROM Tests / FPGA test
Cache bitstreams to GCP
0s
Cache bitstreams to GCP
Verify FPGA jobs
0s
Verify FPGA jobs
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Annotations

13 errors
Build and test software
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Some target names have banned characters.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Process completed with exit code 1.
Lint (slow)
Countermeasure check failed.
Lint (slow)
Process completed with exit code 1.
Earl Grey for CW310 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/25894/merge' exists
Earl Grey for CW310 Hyperdebug / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/25894/merge' exists
Earl Grey for CW340 / Build bitstream
Canceling since a higher priority waiting request for 'CI-refs/pull/25894/merge' exists
Verilated Earl Grey
Canceling since a higher priority waiting request for 'CI-refs/pull/25894/merge' exists
Verilated Earl Grey
The operation was canceled.

Artifacts

Produced during runtime
Name Size
chip_englishbreakfast_cw305
1.39 MB
sw_build_test-test-results
201 Bytes
verilated_englishbreakfast
6.99 MB