[hw,racl,rtl] Disable RaclErrorRsp in case RACL is disabled

Signed-off-by: Robert Schilling <[email protected]>
lowRISC · Jan 29, 2025 · 20f193c · 20f193c
1 parent 6c33a9c
commit 20f193c
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Showing 10 changed files with 39 additions and 37 deletions.
diff --git a/hw/ip/i2c/rtl/i2c.sv b/hw/ip/i2c/rtl/i2c.sv
@@ -12,7 +12,7 @@ module i2c
   parameter logic [NumAlerts-1:0] AlertAsyncOn         = {NumAlerts{1'b1}},
   parameter int unsigned          InputDelayCycles     = 0,
   parameter bit                   EnableRacl           = 1'b0,
-  parameter bit                   RaclErrorRsp         = 1'b1,
+  parameter bit                   RaclErrorRsp         = EnableRacl,
   parameter int unsigned          RaclPolicySelVec[32] = '{32{0}}
 ) (
   input                                    clk_i,

diff --git a/hw/ip/mbx/rtl/mbx.sv b/hw/ip/mbx/rtl/mbx.sv
@@ -15,7 +15,7 @@ module mbx
   parameter bit          DoeIrqSupport            = 1'b1,
   parameter bit          DoeAsyncMsgSupport       = 1'b1,
   parameter bit          EnableRacl               = 1'b0,
-  parameter bit          RaclErrorRsp             = 1'b1,
+  parameter bit          RaclErrorRsp             = EnableRacl,
   parameter int unsigned RaclPolicySelVecSoc[4]   = '{4{0}},
   parameter int unsigned RaclPolicySelWinSocWDATA = 0,
   parameter int unsigned RaclPolicySelWinSocRDATA = 0

diff --git a/hw/ip/pwm/rtl/pwm.sv b/hw/ip/pwm/rtl/pwm.sv
@@ -9,7 +9,7 @@ module pwm
 #(
   parameter logic [NumAlerts-1:0] AlertAsyncOn         = {NumAlerts{1'b1}},
   parameter bit                   EnableRacl           = 1'b0,
-  parameter bit                   RaclErrorRsp         = 1'b1,
+  parameter bit                   RaclErrorRsp         = EnableRacl,
   parameter int unsigned          RaclPolicySelVec[23] = '{23{0}},
   parameter int                   PhaseCntDw           = 16,
   parameter int                   BeatCntDw            = 27

diff --git a/hw/ip/spi_host/rtl/spi_host.sv b/hw/ip/spi_host/rtl/spi_host.sv
@@ -14,7 +14,7 @@ module spi_host
   parameter logic [NumAlerts-1:0] AlertAsyncOn  = {NumAlerts{1'b1}},
   parameter int unsigned          NumCS         = 1,
   parameter bit          EnableRacl             = 1'b0,
-  parameter bit          RaclErrorRsp           = 1'b1,
+  parameter bit          RaclErrorRsp           = EnableRacl,
   parameter int unsigned RaclPolicySelVec[12]   = '{12{0}},
   parameter int unsigned RaclPolicySelWinRXDATA = 0,
   parameter int unsigned RaclPolicySelWinTXDATA = 0

diff --git a/hw/ip/tlul/rtl/tlul_adapter_reg_racl.sv b/hw/ip/tlul/rtl/tlul_adapter_reg_racl.sv
@@ -12,15 +12,15 @@ module tlul_adapter_reg_racl
   import tlul_pkg::*;
   import prim_mubi_pkg::mubi4_t;
 #(
-  parameter  bit CmdIntgCheck      = 0,     // 1: Enable command integrity check
-  parameter  bit EnableRspIntgGen  = 0,     // 1: Generate response integrity
-  parameter  bit EnableDataIntgGen = 0,     // 1: Generate response data integrity
-  parameter  int RegAw             = 8,     // Width of register address
-  parameter  int RegDw             = 32,    // Shall be matched with TL_DW
-  parameter  int AccessLatency     = 0,     // 0: same cycle, 1: next cycle
-  parameter  bit EnableRacl        = 0,     // 1: Enable RACL checks on access
-  parameter  bit RaclErrorRsp      = 1,     // 1: Return TLUL error on RACL errors
-  parameter  int RaclPolicySelVec  = 0,     // RACL policy for this reg adapter
+  parameter  bit CmdIntgCheck      = 0,           // 1: Enable command integrity check
+  parameter  bit EnableRspIntgGen  = 0,           // 1: Generate response integrity
+  parameter  bit EnableDataIntgGen = 0,           // 1: Generate response data integrity
+  parameter  int RegAw             = 8,           // Width of register address
+  parameter  int RegDw             = 32,          // Shall be matched with TL_DW
+  parameter  int AccessLatency     = 0,           // 0: same cycle, 1: next cycle
+  parameter  bit EnableRacl        = 0,           // 1: Enable RACL checks on access
+  parameter  bit RaclErrorRsp      = EnableRacl,  // 1: Return TLUL error on RACL errors
+  parameter  int RaclPolicySelVec  = 0,           // RACL policy for this reg adapter
   localparam int RegBw             = RegDw/8
 ) (
   input clk_i,

diff --git a/hw/ip/tlul/rtl/tlul_adapter_sram_racl.sv b/hw/ip/tlul/rtl/tlul_adapter_sram_racl.sv
@@ -22,25 +22,26 @@ module tlul_adapter_sram_racl
   import prim_mubi_pkg::mubi4_t;
 #(
   parameter int SramAw            = 12,
-  parameter int SramDw            = 32, // Must be multiple of the TL width
-  parameter int Outstanding       = 1,  // Only one request is accepted
-  parameter int SramBusBankAW     = 12, // SRAM bus address width of the SRAM bank. Only used
-                                        // when DataXorAddr=1.
-  parameter bit ByteAccess        = 1,  // 1: Enables sub-word write transactions. Note that this
-                                        //    results in read-modify-write operations for integrity
-                                        //    re-generation if EnableDataIntgPt is set to 1.
-  parameter bit ErrOnWrite        = 0,  // 1: Writes not allowed, automatically error
-  parameter bit ErrOnRead         = 0,  // 1: Reads not allowed, automatically error
-  parameter bit CmdIntgCheck      = 0,  // 1: Enable command integrity check
-  parameter bit EnableRspIntgGen  = 0,  // 1: Generate response integrity
-  parameter bit EnableDataIntgGen = 0,  // 1: Generate response data integrity
-  parameter bit EnableDataIntgPt  = 0,  // 1: Passthrough command/response data integrity
-  parameter bit SecFifoPtr        = 0,  // 1: Duplicated fifo pointers
-  parameter bit EnableReadback    = 0,  // 1: Readback and check written/read data.
-  parameter bit DataXorAddr       = 0,  // 1: XOR data and address for address protection
-  parameter bit EnableRacl        = 0,  // 1: Enable RACL checks on access
-  parameter bit RaclErrorRsp      = 1,  // 1: Return TLUL error on RACL errors
-  parameter int RaclPolicySelVec  = 0,  // RACL policy for this SRAM adapter
+  parameter int SramDw            = 32,         // Must be multiple of the TL width
+  parameter int Outstanding       = 1,          // Only one request is accepted
+  parameter int SramBusBankAW     = 12,         // SRAM bus address width of the SRAM bank. Only
+                                                // used when DataXorAddr=1.
+  parameter bit ByteAccess        = 1,          // 1: Enables sub-word write transactions. Note that
+                                                //    this results in read-modify-write operations
+                                                //    for integrity re-generation if
+                                                //    EnableDataIntgPt is set to 1.
+  parameter bit ErrOnWrite        = 0,          // 1: Writes not allowed, automatically error
+  parameter bit ErrOnRead         = 0,          // 1: Reads not allowed, automatically error
+  parameter bit CmdIntgCheck      = 0,          // 1: Enable command integrity check
+  parameter bit EnableRspIntgGen  = 0,          // 1: Generate response integrity
+  parameter bit EnableDataIntgGen = 0,          // 1: Generate response data integrity
+  parameter bit EnableDataIntgPt  = 0,          // 1: Passthrough command/response data integrity
+  parameter bit SecFifoPtr        = 0,          // 1: Duplicated fifo pointers
+  parameter bit EnableReadback    = 0,          // 1: Readback and check written/read data.
+  parameter bit DataXorAddr       = 0,          // 1: XOR data and address for address protection
+  parameter bit EnableRacl        = 0,          // 1: Enable RACL checks on access
+  parameter bit RaclErrorRsp      = EnableRacl, // 1: Return TLUL error on RACL errors
+  parameter int RaclPolicySelVec  = 0,          // RACL policy for this SRAM adapter
   localparam int WidthMult        = SramDw / top_pkg::TL_DW,
   localparam int IntgWidth        = tlul_pkg::DataIntgWidth * WidthMult,
   localparam int DataOutW         = EnableDataIntgPt ? SramDw + IntgWidth : SramDw

diff --git a/hw/ip/uart/rtl/uart.sv b/hw/ip/uart/rtl/uart.sv
@@ -11,7 +11,7 @@ module uart
 #(
   parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
   parameter bit                   EnableRacl           = 1'b0,
-  parameter bit                   RaclErrorRsp         = 1'b1,
+  parameter bit                   RaclErrorRsp         = EnableRacl,
   parameter int unsigned          RaclPolicySelVec[13] = '{13{0}}
 ) (
   input           clk_i,

diff --git a/hw/ip_templates/ac_range_check/rtl/ac_range_check.sv.tpl b/hw/ip_templates/ac_range_check/rtl/ac_range_check.sv.tpl
@@ -7,7 +7,8 @@ module ${module_instance_name}
   import ${module_instance_name}_reg_pkg::*;
 #(
   parameter logic [NumAlerts-1:0] AlertAsyncOn = {NumAlerts{1'b1}},
-  parameter bit                   RaclErrorRsp = 1'b1,
+  parameter bit                   EnableRacl   = 1'b0,
+  parameter bit                   RaclErrorRsp = EnableRacl,
   parameter int unsigned          RaclPolicySelVec[${3 + 5*num_ranges}] = '{${3 + 5*num_ranges}{0}}
 ) (
   input  logic                                      clk_i,

diff --git a/hw/ip_templates/alert_handler/rtl/alert_handler.sv.tpl b/hw/ip_templates/alert_handler/rtl/alert_handler.sv.tpl
@@ -13,7 +13,7 @@ module ${module_instance_name}
 #(
 % if racl_support:
   parameter bit                   EnableRacl           = 1'b0,
-  parameter bit                   RaclErrorRsp         = 1'b1,
+  parameter bit                   RaclErrorRsp         = EnableRacl,
 <% 
 num_regs = 6 + 4 * n_alerts + 4 * 7 + n_classes * 14
 %>\

diff --git a/hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl b/hw/ip_templates/rv_plic/rtl/rv_plic.sv.tpl
@@ -25,8 +25,8 @@ module ${module_instance_name} import ${module_instance_name}_reg_pkg::*; #(
   // and routing the source clocks / resets to the PLIC).
   parameter logic [NumSrc-1:0]    LevelEdgeTrig = '0, // 0: level, 1: edge
 % if racl_support:
-  parameter bit                   EnableRacl           = 1'b0,
-  parameter bit                   RaclErrorRsp         = 1'b1,
+  parameter bit                   EnableRacl    = 1'b0,
+  parameter bit                   RaclErrorRsp  = EnableRacl,
 <% 
 from math import ceil
 num_regs = src + ceil(src / 32) + target * ceil(src / 32) + 3 * target + 1