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Fix expected storage classes for reference catalogs.
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These are currently ignored by overly-permissive checks in pipe_base,
but this will soon be fixed.
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TallJimbo committed Jul 24, 2023
1 parent e3432ed commit 770c810
Showing 1 changed file with 14 additions and 14 deletions.
28 changes: 14 additions & 14 deletions tests/test_pipelines.py
Original file line number Diff line number Diff line change
Expand Up @@ -185,8 +185,8 @@ def test_decam_drp_merian(self):
os.path.join(PIPELINES_DIR, "DECam", "DRP-Merian.yaml"),
["#step0"],
[
("ps1_pv3_3pi_20170110", {"htm7"}, "Catalog", False),
("gaia_dr2_20200414", {"htm7"}, "Catalog", False),
("ps1_pv3_3pi_20170110", {"htm7"}, "SimpleCatalog", False),
("gaia_dr2_20200414", {"htm7"}, "SimpleCatalog", False),
],
expected_inputs={
"camera",
Expand All @@ -206,8 +206,8 @@ def test_decam_drp_merian(self):
"#step3",
],
[
("ps1_pv3_3pi_20170110", {"htm7"}, "Catalog", False),
("gaia_dr2_20200414", {"htm7"}, "Catalog", False),
("ps1_pv3_3pi_20170110", {"htm7"}, "SimpleCatalog", False),
("gaia_dr2_20200414", {"htm7"}, "SimpleCatalog", False),
],
expected_inputs=COMMON_INPUTS
| {
Expand Down Expand Up @@ -236,8 +236,8 @@ def test_hsc_drp_ci_hsc(self):
os.path.join(PIPELINES_DIR, "HSC", "DRP-ci_hsc.yaml"),
[""],
[
("ps1_pv3_3pi_20170110", {"htm7"}, "Catalog", False),
("gaia_dr2_20200414", {"htm7"}, "Catalog", False),
("ps1_pv3_3pi_20170110", {"htm7"}, "SimpleCatalog", False),
("gaia_dr2_20200414", {"htm7"}, "SimpleCatalog", False),
],
expected_inputs=COMMON_INPUTS
| HSC_INPUTS
Expand Down Expand Up @@ -291,8 +291,8 @@ def test_hsc_drp_prod(self):
"#step7",
],
[
("ps1_pv3_3pi_20170110", {"htm7"}, "Catalog", False),
("gaia_dr2_20200414", {"htm7"}, "Catalog", False),
("ps1_pv3_3pi_20170110", {"htm7"}, "SimpleCatalog", False),
("gaia_dr2_20200414", {"htm7"}, "SimpleCatalog", False),
],
expected_inputs=COMMON_INPUTS | HSC_INPUTS | {"fgcmLookUpTable"},
expected_outputs=COMMON_OUTPUTS
Expand Down Expand Up @@ -339,8 +339,8 @@ def test_hsc_drp_rc2(self):
"#step7",
],
[
("ps1_pv3_3pi_20170110", {"htm7"}, "Catalog", False),
("gaia_dr2_20200414", {"htm7"}, "Catalog", False),
("ps1_pv3_3pi_20170110", {"htm7"}, "SimpleCatalog", False),
("gaia_dr2_20200414", {"htm7"}, "SimpleCatalog", False),
],
expected_inputs=COMMON_INPUTS | HSC_INPUTS | {"fgcmLookUpTable"},
expected_outputs=COMMON_OUTPUTS
Expand Down Expand Up @@ -406,8 +406,8 @@ def test_hsc_drp_rc2_subset(self):
"#nightlyStep5",
],
[
("ps1_pv3_3pi_20170110", {"htm7"}, "Catalog", False),
("gaia_dr2_20200414", {"htm7"}, "Catalog", False),
("ps1_pv3_3pi_20170110", {"htm7"}, "SimpleCatalog", False),
("gaia_dr2_20200414", {"htm7"}, "SimpleCatalog", False),
],
expected_inputs=COMMON_INPUTS | HSC_INPUTS | {"fgcmLookUpTable"},
expected_outputs=COMMON_OUTPUTS
Expand Down Expand Up @@ -440,7 +440,7 @@ def test_lsstcam_imsim_drp_ci_imsim(self):
os.path.join(PIPELINES_DIR, "LSSTCam-imSim", "DRP-ci_imsim.yaml"),
[f"#step{N}" for N in range(1, 9)],
[
("cal_ref_cat_2_2", {"htm7"}, "Catalog", False),
("cal_ref_cat_2_2", {"htm7"}, "SimpleCatalog", False),
],
expected_inputs=COMMON_INPUTS | LSSTCAM_IMSIM_INPUTS,
expected_outputs=COMMON_OUTPUTS | LSSTCAM_IMSIM_OUTPUTS,
Expand All @@ -453,7 +453,7 @@ def test_lsstcam_imsim_drp_test_med_1(self):
os.path.join(PIPELINES_DIR, "LSSTCam-imSim", "DRP-test-med-1.yaml"),
[f"#step{N}" for N in range(1, 9)],
[
("cal_ref_cat_2_2", {"htm7"}, "Catalog", False),
("cal_ref_cat_2_2", {"htm7"}, "SimpleCatalog", False),
],
expected_inputs=COMMON_INPUTS | LSSTCAM_IMSIM_INPUTS,
expected_outputs=COMMON_OUTPUTS | LSSTCAM_IMSIM_OUTPUTS,
Expand Down

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