add Maia SDR to ant and e200

This adds Maia SDR to the ant and e200 patchsets. All the existing ADI infrastructure is preserved, with maia-hdl piggybacking on the same ADC inputs. This makes it possible to use Maia SDR and IIO at the same time, with the only drawback of Maia SDR taking up 400 MiB of reserved memory for the IQ recorder. Signed-off-by: Daniel Estévez <[email protected]>
maia-sdr · Dec 16, 2023 · 99a01bd · 99a01bd
1 parent 762490e
commit 99a01bd
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diff --git a/.gitmodules b/.gitmodules
@@ -2,3 +2,6 @@
 	path = plutosdr-fw
 	url = https://github.com/analogdevicesinc/plutosdr-fw
 	branch = "v0.38"
+[submodule "maia-sdr"]
+	path = maia-sdr
+	url = https://github.com/maia-sdr/maia-sdr
diff --git a/maia-sdr b/maia-sdr
diff --git a/patch/0002-add-maia-sdr-hdl-support-v0.38.patch b/patch/0002-add-maia-sdr-hdl-support-v0.38.patch
@@ -0,0 +1,307 @@
+From 3fc9ddf2ee20f3fbe0fecf198c6b8f38c27305ad Mon Sep 17 00:00:00 2001
+From: =?UTF-8?q?Daniel=20Est=C3=A9vez?= <[email protected]>
+Date: Thu, 14 Dec 2023 18:00:00 +0100
+Subject: [PATCH] add maia sdr hdl support
+
+---
+ projects/ant/Makefile       |  7 ++++
+ projects/ant/system_bd.tcl  | 76 ++++++++++++++++++++++++++++++-------
+ projects/e200/Makefile      |  7 ++++
+ projects/e200/system_bd.tcl | 75 +++++++++++++++++++++++++++++-------
+ 4 files changed, 137 insertions(+), 28 deletions(-)
+
+diff --git a/projects/ant/Makefile b/projects/ant/Makefile
+index 4a1ad7e0f..147a9220b 100644
+--- a/projects/ant/Makefile
++++ b/projects/ant/Makefile
+@@ -14,6 +14,8 @@ M_DEPS += ../../library/common/ad_iobuf.v
+ M_DEPS += ../../library/common/ad_bus_mux.v
+ M_DEPS += ../../library/axi_tdd/scripts/axi_tdd.tcl
+ M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl
++# Maia SDR IP cores
++M_DEPS += ip_cores
+
+ LIB_DEPS += axi_ad9361
+ LIB_DEPS += axi_dmac
+@@ -22,3 +24,8 @@ LIB_DEPS += util_pack/util_cpack2
+ LIB_DEPS += util_pack/util_upack2
+
+ include ../scripts/project-xilinx.mk
++
++ip_cores:
++	$(MAKE) -C ../../../../maia-sdr/maia-hdl/ip/
++
++.PHONY: ip_cores
+diff --git a/projects/ant/system_bd.tcl b/projects/ant/system_bd.tcl
+index ad924fcc1..4564f8d69 100644
+--- a/projects/ant/system_bd.tcl
++++ b/projects/ant/system_bd.tcl
+@@ -1,9 +1,14 @@
+ # create board design
+
++# Add IP repo path for Maia SDR
++#
++# We need to do this here because adi_project_create overwrites whatever we had
++# set beforehand.
++set_property ip_repo_paths "../../../../maia-sdr/maia-hdl/ip/ $ad_hdl_dir/library" [current_fileset]
++update_ip_catalog
++
+ source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
+ source $ad_hdl_dir/library/axi_tdd/scripts/axi_tdd.tcl
+-set_property  ip_repo_paths  $ad_hdl_dir/library/ [current_project]
+-update_ip_catalog
+
+ # default ports
+
+@@ -218,6 +223,35 @@ ad_add_decimation_filter "rx_fir_decimator" 8 2 1 {61.44} {61.44} \
+ ad_ip_instance xlslice decim_slice
+ ad_ip_instance util_cpack2 cpack
+
++# Maia SDR core
++
++ad_ip_instance maia_sdr maia_sdr
++
++ad_ip_instance xlslice adc_i_slice
++ad_ip_parameter adc_i_slice CONFIG.DIN_WIDTH 16
++ad_ip_parameter adc_i_slice CONFIG.DOUT_WIDTH 12
++ad_ip_parameter adc_i_slice CONFIG.DIN_FROM 11
++
++ad_ip_instance xlslice adc_q_slice
++ad_ip_parameter adc_q_slice CONFIG.DIN_TO 0
++ad_ip_parameter adc_q_slice CONFIG.DIN_WIDTH 16
++ad_ip_parameter adc_q_slice CONFIG.DOUT_WIDTH 12
++ad_ip_parameter adc_q_slice CONFIG.DIN_FROM 11
++
++# Maia SDR clocking
++
++create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 maia_sdr_clk
++set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} CONFIG.ENABLE_CLOCK_MONITOR {false} CONFIG.PRIM_SOURCE {Global_buffer} \
++                        CONFIG.CLKOUT2_USED {true} CONFIG.CLKOUT3_USED {true} CONFIG.NUM_OUT_CLKS {3} \
++                        CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {62.500} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125.000} \
++                        CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {187.5} \
++                        CONFIG.PRIMITIVE {MMCM} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {11.250} \
++                        CONFIG.MMCM_CLKOUT0_DIVIDE_F {18.000} CONFIG.MMCM_CLKOUT1_DIVIDE {9} \
++                        CONFIG.MMCM_CLKOUT3_DIVIDE {6} \
++                        CONFIG.CLKOUT1_JITTER {133.663} CONFIG.CLKOUT1_PHASE_ERROR {91.100} \
++                        CONFIG.CLKOUT2_JITTER {116.571} CONFIG.CLKOUT2_PHASE_ERROR {91.100} \
++                        CONFIG.CLKOUT3_JITTER {108.217} CONFIG.CLKOUT3_PHASE_ERROR {91.100}] [get_bd_cells maia_sdr_clk]
++
+ # connections
+
+ ad_connect  rx_clk_in axi_ad9361/rx_clk_in
+@@ -301,6 +335,22 @@ ad_connect  axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk
+ ad_connect  axi_ad9361/l_clk axi_ad9361_dac_dma/m_axis_aclk
+ ad_connect  cpack/fifo_wr_overflow axi_ad9361/adc_dovf
+
++# Maia SDR connections
++
++ad_connect  axi_ad9361/adc_data_i0 adc_i_slice/Din
++ad_connect  axi_ad9361/adc_data_q0 adc_q_slice/Din
++ad_connect  adc_i_slice/Dout maia_sdr/re_in
++ad_connect  adc_q_slice/Dout maia_sdr/im_in
++ad_connect  axi_ad9361/l_clk maia_sdr/sampling_clk
++ad_connect  sys_cpu_clk maia_sdr/s_axi_lite_clk
++ad_connect  sys_cpu_reset maia_sdr/s_axi_lite_rst
++ad_connect  maia_sdr_clk/clk_out1 maia_sdr/clk
++ad_connect  maia_sdr_clk/clk_out2 maia_sdr/clk2x_clk
++ad_connect  maia_sdr_clk/clk_out3 maia_sdr/clk3x_clk
++
++ad_connect  sys_cpu_clk maia_sdr_clk/clk_in1
++ad_connect  sys_cpu_reset maia_sdr_clk/reset
++
+ # External TDD
+ set TDD_CHANNEL_CNT 3
+ set TDD_DEFAULT_POL 0b010
+@@ -344,28 +394,24 @@ ad_cpu_interconnect 0x79020000 axi_ad9361
+ ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
+ ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
+ ad_cpu_interconnect 0x7C440000 axi_tdd_0
++ad_cpu_interconnect 0x7C460000 maia_sdr
+ ad_cpu_interconnect 0x43C00000 axi_vcxo_ctrl
+
+ ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1}
+-ad_connect sys_cpu_clk sys_ps7/S_AXI_HP1_ACLK
+-ad_connect axi_ad9361_adc_dma/m_dest_axi sys_ps7/S_AXI_HP1
++ad_connect maia_sdr_clk/clk_out1 sys_ps7/S_AXI_HP1_ACLK
++ad_connect maia_sdr/m_axi_spectrometer sys_ps7/S_AXI_HP1
+
+ create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \
+-                    [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] \
++                    [get_bd_addr_spaces maia_sdr/m_axi_spectrometer] \
+                     [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] \
+                     SEG_sys_ps7_HP1_DDR_LOWOCM
+
+ ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 {1}
+-ad_connect sys_cpu_clk sys_ps7/S_AXI_HP2_ACLK
+-ad_connect axi_ad9361_dac_dma/m_src_axi sys_ps7/S_AXI_HP2
++ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
++ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
++ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
++ad_mem_hp2_interconnect sys_cpu_clk maia_sdr/m_axi_recorder
+
+-create_bd_addr_seg -range 0x40000000 -offset 0x00000000 \
+-                    [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] \
+-                    [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] \
+-                    SEG_sys_ps7_HP2_DDR_LOWOCM
+-
+-ad_connect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi_aclk
+-ad_connect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi_aclk
+ ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
+ ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
+
+@@ -373,4 +419,6 @@ ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
+
+ ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
+ ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
++ad_cpu_interrupt ps-11 mb-11 maia_sdr/interrupt_out
++
+
+diff --git a/projects/e200/Makefile b/projects/e200/Makefile
+index 1c9b4f2f4..de002f2fa 100644
+--- a/projects/e200/Makefile
++++ b/projects/e200/Makefile
+@@ -14,6 +14,8 @@ M_DEPS += ../../library/common/ad_iobuf.v
+ M_DEPS += ../../library/common/ad_bus_mux.v
+ M_DEPS += ../../library/axi_tdd/scripts/axi_tdd.tcl
+ M_DEPS += ../../library/axi_ad9361/axi_ad9361_delay.tcl
++# Maia SDR IP cores
++M_DEPS += ip_cores
+
+ LIB_DEPS += axi_ad9361
+ LIB_DEPS += axi_dmac
+@@ -23,3 +25,8 @@ LIB_DEPS += util_pack/util_upack2
+
+
+ include ../scripts/project-xilinx.mk
++
++ip_cores:
++	$(MAKE) -C ../../../../maia-sdr/maia-hdl/ip/
++
++.PHONY: ip_cores
+diff --git a/projects/e200/system_bd.tcl b/projects/e200/system_bd.tcl
+index 9926d22a7..290fb3954 100644
+--- a/projects/e200/system_bd.tcl
++++ b/projects/e200/system_bd.tcl
+@@ -1,9 +1,14 @@
+ # create board design
+
++# Add IP repo path for Maia SDR
++#
++# We need to do this here because adi_project_create overwrites whatever we had
++# set beforehand.
++set_property ip_repo_paths "../../../../maia-sdr/maia-hdl/ip/ $ad_hdl_dir/library" [current_fileset]
++update_ip_catalog
++
+ source $ad_hdl_dir/projects/common/xilinx/adi_fir_filter_bd.tcl
+ source $ad_hdl_dir/library/axi_tdd/scripts/axi_tdd.tcl
+-set_property  ip_repo_paths  $ad_hdl_dir/library/ [current_project]
+-update_ip_catalog
+
+ # default ports
+
+@@ -247,6 +252,35 @@ ad_add_decimation_filter "rx_fir_decimator" 8 2 1 {61.44} {61.44} \
+ ad_ip_instance xlslice decim_slice
+ ad_ip_instance util_cpack2 cpack
+
++# Maia SDR core
++
++ad_ip_instance maia_sdr maia_sdr
++
++ad_ip_instance xlslice adc_i_slice
++ad_ip_parameter adc_i_slice CONFIG.DIN_WIDTH 16
++ad_ip_parameter adc_i_slice CONFIG.DOUT_WIDTH 12
++ad_ip_parameter adc_i_slice CONFIG.DIN_FROM 11
++
++ad_ip_instance xlslice adc_q_slice
++ad_ip_parameter adc_q_slice CONFIG.DIN_TO 0
++ad_ip_parameter adc_q_slice CONFIG.DIN_WIDTH 16
++ad_ip_parameter adc_q_slice CONFIG.DOUT_WIDTH 12
++ad_ip_parameter adc_q_slice CONFIG.DIN_FROM 11
++
++# Maia SDR clocking
++
++create_bd_cell -type ip -vlnv xilinx.com:ip:clk_wiz:6.0 maia_sdr_clk
++set_property -dict [list CONFIG.USE_PHASE_ALIGNMENT {false} CONFIG.ENABLE_CLOCK_MONITOR {false} CONFIG.PRIM_SOURCE {Global_buffer} \
++                        CONFIG.CLKOUT2_USED {true} CONFIG.CLKOUT3_USED {true} CONFIG.NUM_OUT_CLKS {3} \
++                        CONFIG.CLKOUT1_REQUESTED_OUT_FREQ {62.500} CONFIG.CLKOUT2_REQUESTED_OUT_FREQ {125.000} \
++                        CONFIG.CLKOUT3_REQUESTED_OUT_FREQ {187.5} \
++                        CONFIG.PRIMITIVE {MMCM} CONFIG.MMCM_DIVCLK_DIVIDE {1} CONFIG.MMCM_CLKFBOUT_MULT_F {11.250} \
++                        CONFIG.MMCM_CLKOUT0_DIVIDE_F {18.000} CONFIG.MMCM_CLKOUT1_DIVIDE {9} \
++                        CONFIG.MMCM_CLKOUT3_DIVIDE {6} \
++                        CONFIG.CLKOUT1_JITTER {133.663} CONFIG.CLKOUT1_PHASE_ERROR {91.100} \
++                        CONFIG.CLKOUT2_JITTER {116.571} CONFIG.CLKOUT2_PHASE_ERROR {91.100} \
++                        CONFIG.CLKOUT3_JITTER {108.217} CONFIG.CLKOUT3_PHASE_ERROR {91.100}] [get_bd_cells maia_sdr_clk]
++
+ # connections
+
+ ad_connect  rx_clk_in axi_ad9361/rx_clk_in
+@@ -330,6 +364,22 @@ ad_connect  axi_ad9361/l_clk axi_ad9361_adc_dma/fifo_wr_clk
+ ad_connect  axi_ad9361/l_clk axi_ad9361_dac_dma/m_axis_aclk
+ ad_connect  cpack/fifo_wr_overflow axi_ad9361/adc_dovf
+
++# Maia SDR connections
++
++ad_connect  axi_ad9361/adc_data_i0 adc_i_slice/Din
++ad_connect  axi_ad9361/adc_data_q0 adc_q_slice/Din
++ad_connect  adc_i_slice/Dout maia_sdr/re_in
++ad_connect  adc_q_slice/Dout maia_sdr/im_in
++ad_connect  axi_ad9361/l_clk maia_sdr/sampling_clk
++ad_connect  sys_cpu_clk maia_sdr/s_axi_lite_clk
++ad_connect  sys_cpu_reset maia_sdr/s_axi_lite_rst
++ad_connect  maia_sdr_clk/clk_out1 maia_sdr/clk
++ad_connect  maia_sdr_clk/clk_out2 maia_sdr/clk2x_clk
++ad_connect  maia_sdr_clk/clk_out3 maia_sdr/clk3x_clk
++
++ad_connect  sys_cpu_clk maia_sdr_clk/clk_in1
++ad_connect  sys_cpu_reset maia_sdr_clk/reset
++
+ # External TDD
+ set TDD_CHANNEL_CNT 3
+ set TDD_DEFAULT_POL 0b010
+@@ -373,28 +423,24 @@ ad_cpu_interconnect 0x79020000 axi_ad9361
+ ad_cpu_interconnect 0x7C400000 axi_ad9361_adc_dma
+ ad_cpu_interconnect 0x7C420000 axi_ad9361_dac_dma
+ ad_cpu_interconnect 0x7C440000 axi_tdd_0
++ad_cpu_interconnect 0x7C460000 maia_sdr
+ ad_cpu_interconnect 0x43C00000 axi_vcxo_ctrl
+
+ ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP1 {1}
+-ad_connect sys_cpu_clk sys_ps7/S_AXI_HP1_ACLK
+-ad_connect axi_ad9361_adc_dma/m_dest_axi sys_ps7/S_AXI_HP1
++ad_connect maia_sdr_clk/clk_out1 sys_ps7/S_AXI_HP1_ACLK
++ad_connect maia_sdr/m_axi_spectrometer sys_ps7/S_AXI_HP1
+
+ create_bd_addr_seg -range 0x20000000 -offset 0x00000000 \
+-                    [get_bd_addr_spaces axi_ad9361_adc_dma/m_dest_axi] \
++                    [get_bd_addr_spaces maia_sdr/m_axi_spectrometer] \
+                     [get_bd_addr_segs sys_ps7/S_AXI_HP1/HP1_DDR_LOWOCM] \
+                     SEG_sys_ps7_HP1_DDR_LOWOCM
+
+ ad_ip_parameter sys_ps7 CONFIG.PCW_USE_S_AXI_HP2 {1}
+-ad_connect sys_cpu_clk sys_ps7/S_AXI_HP2_ACLK
+-ad_connect axi_ad9361_dac_dma/m_src_axi sys_ps7/S_AXI_HP2
+-
+-create_bd_addr_seg -range 0x20000000 -offset 0x00000000 \
+-                    [get_bd_addr_spaces axi_ad9361_dac_dma/m_src_axi] \
+-                    [get_bd_addr_segs sys_ps7/S_AXI_HP2/HP2_DDR_LOWOCM] \
+-                    SEG_sys_ps7_HP2_DDR_LOWOCM
++ad_mem_hp2_interconnect sys_cpu_clk sys_ps7/S_AXI_HP2
++ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi
++ad_mem_hp2_interconnect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi
++ad_mem_hp2_interconnect sys_cpu_clk maia_sdr/m_axi_recorder
+
+-ad_connect sys_cpu_clk axi_ad9361_dac_dma/m_src_axi_aclk
+-ad_connect sys_cpu_clk axi_ad9361_adc_dma/m_dest_axi_aclk
+ ad_connect sys_cpu_resetn axi_ad9361_adc_dma/m_dest_axi_aresetn
+ ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
+
+@@ -402,5 +448,6 @@ ad_connect sys_cpu_resetn axi_ad9361_dac_dma/m_src_axi_aresetn
+
+ ad_cpu_interrupt ps-13 mb-13 axi_ad9361_adc_dma/irq
+ ad_cpu_interrupt ps-12 mb-12 axi_ad9361_dac_dma/irq
++ad_cpu_interrupt ps-11 mb-11 maia_sdr/interrupt_out
+
+
+-- 
+2.43.0
+