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Add partial XHCI support
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This enables the first two DWC3 controllers in host mode (bottom USB-A and Type-C on the ROCK5B).
SuperSpeed is disabled for now.

Also switch to XhciDxe and EhciDxe from MdeModulePkg and disable OHCI.
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mariobalanica committed Mar 10, 2023
1 parent c82240a commit 05ae220
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Showing 9 changed files with 626 additions and 14 deletions.
2 changes: 2 additions & 0 deletions edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Dsdt.asl
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Expand Up @@ -107,5 +107,7 @@ DefinitionBlock ("Dsdt.aml", "DSDT", 2, "RPIFDN", "RPI", 2)

// won't work on Windows, will trigger bugcheck by usbehci
// include ("Usb2.asl")

include ("Usb3.asl")
}
}
54 changes: 54 additions & 0 deletions edk2-platforms/Platform/Radxa/ROCK5B/AcpiTables/Usb3.asl
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@@ -0,0 +1,54 @@
/** @file
* DWC3 XHCI Controllers.
*
* Copyright (c) 2023, Mario Bălănică <[email protected]>
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
**/

#include "AcpiTables.h"

Device (XHC0) {
Name (_HID, "PNP0D10")
Name (_UID, Zero)
Name (_CCA, Zero)

Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfc000000, 0x400000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 252 }
})
Return (RBUF)
}
}

Device (XHC1) {
Name (_HID, "PNP0D10")
Name (_UID, One)
Name (_CCA, Zero)

Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfc400000, 0x400000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 253 }
})
Return (RBUF)
}
}

// TODO: This requires set up of the Naneng Combo PIPE PHY2
// USB2 DP / DM are connected to one of the EHCI controllers instead (EHC1 on ROCK 5B).
/*
Device (XHC2) {
Name (_HID, "PNP0D10")
Name (_UID, Two)
Name (_CCA, Zero)
Method (_CRS, 0x0, Serialized) {
Name (RBUF, ResourceTemplate() {
Memory32Fixed (ReadWrite, 0xfcd00000, 0x400000)
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) { 254 }
})
Return (RBUF)
}
}*/
Original file line number Diff line number Diff line change
Expand Up @@ -209,6 +209,7 @@ void
EFIAPI
Usb2PhyResume (void)
{
MmioWrite32(0xfd5d0008, 0x20000000);
MmioWrite32(0xfd5d4008, 0x20000000);
MmioWrite32(0xfd5d8008, 0x20000000);
MmioWrite32(0xfd5dc008, 0x20000000);
Expand All @@ -218,12 +219,13 @@ Usb2PhyResume (void)

void
EFIAPI
UdPhyU3PortDisable (void)
UsbDpPhyEnable (void)
{
/* disable U3 port */
MmioWrite32 (0xfd5ac01c, 0xf08d0089);
MmioWrite32 (0xfd5ac034, 0xf08d0089);
/* remove rx-termination */
/* enable rx_lfps_en & usbdp_low_pwrn */
MmioWrite32(0xfd5c8004, 0x60006000);
MmioWrite32(0xfd5cc004, 0x60006000);

/* remove rx-termination, we don't support SS yet */
MmioWrite32 (0xfd5c800c, 0x00030001);
MmioWrite32 (0xfd5cc00c, 0x00030001);
}
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9 changes: 5 additions & 4 deletions edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.dsc
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Expand Up @@ -453,25 +453,26 @@
#
Platform/Radxa/ROCK5B/Drivers/PlatformSmbiosDxe/PlatformSmbiosDxe.inf
MdeModulePkg/Universal/SmbiosDxe/SmbiosDxe.inf

#
# USB Ohci Controller
#
Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
#Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf

#
# USB Ehci Controller
#
Silicon/Rockchip/Drivers/EhciDxe/EhciDxe.inf
MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf

#
# USB Dwc3 Controller
#
Silicon/Rockchip/Drivers/UsbDwc3InitDxe/UsbDwc3.inf
Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf

#
# USB Xhci Controller
#
Silicon/Rockchip/Drivers/XhciDxe/XhciDxe.inf
MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf

#
# USB Host Support
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8 changes: 4 additions & 4 deletions edk2-platforms/Platform/Radxa/ROCK5B/ROCK5B.fdf
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Expand Up @@ -178,22 +178,22 @@ READ_LOCK_STATUS = TRUE
#
# USB Ehci Controller
#
INF Silicon/Rockchip/Drivers/EhciDxe/EhciDxe.inf
INF MdeModulePkg/Bus/Pci/EhciDxe/EhciDxe.inf

#
# USB Ohci Controller
#
INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf
#INF Silicon/Rockchip/Drivers/OhciDxe/OhciDxe.inf

#
# USB Dwc3 Controller
#
INF Silicon/Rockchip/Drivers/UsbDwc3InitDxe/UsbDwc3.inf
INF Silicon/Rockchip/Drivers/UsbHcdInitDxe/UsbHcd.inf

#
# USB Xhci Controller
#
INF Silicon/Rockchip/Drivers/XhciDxe/XhciDxe.inf
INF MdeModulePkg/Bus/Pci/XhciDxe/XhciDxe.inf

#
# USB Host Support
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