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Format and fix lint errors
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@mattgodbolt
mattgodbolt committed Dec 4, 2023
1 parent e24e8f9 commit 4765906
Showing 1 changed file with 23 additions and 29 deletions.
52 changes: 23 additions & 29 deletions tube.js
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Original file line number Diff line number Diff line change
Expand Up @@ -48,14 +48,9 @@ export class Tube {
new Uint8Array(TUBE_ULA_R1_PARASITE_BYTE_COUNT),
new Uint8Array(1),
new Uint8Array(2),
new Uint8Array(1)
];
this.hostToParasiteData = [
new Uint8Array(1),
new Uint8Array(1),
new Uint8Array(2),
new Uint8Array(1)
];
this.hostToParasiteData = [new Uint8Array(1), new Uint8Array(1), new Uint8Array(2), new Uint8Array(1)];
this.parasiteToHostFifoByteCount1 = 0;
this.parasiteToHostFifoByteCount3 = 0;
this.hostToParasiteFifoByteCount3 = 0;
Expand All @@ -68,7 +63,7 @@ export class Tube {
for (let i = 0; i < 4; i++) {
this.hostStatus[i] = TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL;
this.parasiteStatus[i] = TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL;
if (i == TUBE_ULA_R3) {
if (i === TUBE_ULA_R3) {
// register 3 has one valid but insignificant byte in the parasite to host FIFO (this is to prevent an immediate PNMI state after PRST)
this.hostStatus[i] |= TUBE_ULA_FLAG_DATA_AVAILABLE;
this.parasiteToHostData[i][0] = 0;
Expand All @@ -83,23 +78,19 @@ export class Tube {
updateInterrupts() {
// host IRQ
if (
(this.hostStatus[TUBE_ULA_R4] & TUBE_ULA_FLAG_DATA_AVAILABLE) &&
(this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_HOST_IRQ_FROM_R4_DATA)
this.hostStatus[TUBE_ULA_R4] & TUBE_ULA_FLAG_DATA_AVAILABLE &&
this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_HOST_IRQ_FROM_R4_DATA
) {
this.hostCpu.interrupt |= HOST_CPU_FLAG_IRQ_TUBE_ULA;
} else {
this.hostCpu.interrupt &= ~HOST_CPU_FLAG_IRQ_TUBE_ULA;
}
// parasite IRQ
if (
(
(this.parasiteStatus[TUBE_ULA_R1] & TUBE_ULA_FLAG_DATA_AVAILABLE) &&
(this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_PARASITE_IRQ_FROM_R1_DATA)
) ||
(
(this.parasiteStatus[TUBE_ULA_R4] & TUBE_ULA_FLAG_DATA_AVAILABLE) &&
(this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_PARASITE_IRQ_FROM_R4_DATA)
)
(this.parasiteStatus[TUBE_ULA_R1] & TUBE_ULA_FLAG_DATA_AVAILABLE &&
this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_PARASITE_IRQ_FROM_R1_DATA) ||
(this.parasiteStatus[TUBE_ULA_R4] & TUBE_ULA_FLAG_DATA_AVAILABLE &&
this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_PARASITE_IRQ_FROM_R4_DATA)
) {
this.parasiteCpu.interrupt = true;
} else {
Expand All @@ -112,27 +103,27 @@ export class Tube {
// register 3)
// or: M = 1, V = 1, 2 bytes in host to parasite register 3 FIFO or 0 bytes in parasite to host
// register 3 FIFO. (this allows two byte transfers across register 3)
const r3Size = (this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_2_BYTE_R3_DATA) ? 2 : 1;
const r3Size = this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_2_BYTE_R3_DATA ? 2 : 1;
if (
(this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_PARASITE_NMI_FROM_R3_DATA) &&
(
(this.hostToParasiteFifoByteCount3 >= r3Size) ||
(this.parasiteToHostFifoByteCount3 === 0)
)
this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_ENABLE_PARASITE_NMI_FROM_R3_DATA &&
(this.hostToParasiteFifoByteCount3 >= r3Size || this.parasiteToHostFifoByteCount3 === 0)
) {
this.parasiteCpu.nmi = true;
} else {
this.parasiteCpu.nmi = false;
}
// parasite CPU RESET held low - not implemented in the CPU - the CPU should be frozen until this signal is released
this.parasiteCpu.resetHeldLow = (this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_PARASITE_RESET_ACTIVE_LOW);
this.parasiteCpu.resetHeldLow = this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_PARASITE_RESET_ACTIVE_LOW;
}
hostRead(address) {
let result = 0xfe;
switch (address & 7) {
case TUBE_ULA_R1_STATUS_ADDRESS:
result = (this.hostStatus[TUBE_ULA_R1] & (TUBE_ULA_FLAG_DATA_AVAILABLE | TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL)) |
(this.internalStatusRegister & ~(TUBE_ULA_FLAG_DATA_AVAILABLE | TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL));
result =
(this.hostStatus[TUBE_ULA_R1] &
(TUBE_ULA_FLAG_DATA_AVAILABLE | TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL)) |
(this.internalStatusRegister &
~(TUBE_ULA_FLAG_DATA_AVAILABLE | TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL));
break;
case TUBE_ULA_R1_DATA_ADDRESS:
result = this.parasiteToHostData[TUBE_ULA_R1][0];
Expand Down Expand Up @@ -191,9 +182,12 @@ export class Tube {
switch (address & 7) {
case TUBE_ULA_R1_STATUS_ADDRESS:
if (value & TUBE_ULA_FLAG_STATUS_SET_CONTROL_FLAGS) {
this.internalStatusRegister |= (value & ~(TUBE_ULA_FLAG_DATA_AVAILABLE | TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL));
this.internalStatusRegister |=
value & ~(TUBE_ULA_FLAG_DATA_AVAILABLE | TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL);
} else {
this.internalStatusRegister &= ~(value & ~(TUBE_ULA_FLAG_DATA_AVAILABLE | TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL));
this.internalStatusRegister &= ~(
value & ~(TUBE_ULA_FLAG_DATA_AVAILABLE | TUBE_ULA_FLAG_DATA_REGISTER_NOT_FULL)
);
}
if (value & TUBE_ULA_FLAG_STATUS_CLEAR_ALL_TUBE_REGISTERS) {
this.reset(false);
Expand All @@ -203,7 +197,7 @@ export class Tube {
// it prints the startup banner but then seems to stop responding when a R3 data
// transfer (based on Advanced User Guide example) is attempted
if (this.internalStatusRegister & TUBE_ULA_FLAG_STATUS_PARASITE_RESET_ACTIVE_LOW) {
this.parasiteCpu.reset(true); // this in turn calls our this.reset(true)
this.parasiteCpu.reset(true); // this in turn calls our this.reset(true)
}
}
break;
Expand Down

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