Squashed commit of the following:

commit 5ec0fc859f017654144b33cfad92bbae62391088 Author: Captain Jack Sparrow <[email protected]> Date: Mon Apr 17 18:37:24 2023 +0000 Merged PR 3211: Upgrade hatlib dependency to 0.0.39 Upgrade hatlib dependency to 0.0.39 commit 38642006cbc8c4ff01c7345d018f9a8233454dbd Author: Mason Remy <[email protected]> Date: Fri Apr 14 19:27:01 2023 +0000 Merged PR 3209: Support AffineParallelOp and scf::ParallelOp in RangeValue utils Support AffineParallelOp and scf::ParallelOp in RangeValue utils commit addb45a1a4ccb50657b822591735916be83498c5 Author: Captain Jack Sparrow <[email protected]> Date: Wed Apr 12 17:25:02 2023 +0000 Merged PR 3207: Fix parallelization and enable file checker in tests Fix parallelization and enable file checker in tests commit 7e206532932ff603decfd46656173702ebdceff5 Author: Lisa Ong <[email protected]> Date: Wed Apr 12 08:02:20 2023 +0000 Merged PR 3195: [LLVM 15] progressive upgrade (24a37a396a9b), disable macos builds The first of a series of progressive upgrades from LLVM 14.0.6 to LLVM 15.0.7 (and possibly beyond). Current LLVM version: https://intelligentdevices.visualstudio.com/ELL/_git/accera.llvm?version=GBaccera/llvmorg-15-24a37a396a9b&_a=history This is llvmorg-15.0.0-init, fast forwarded to about 100 "relevant" MLIR commits (actual number of commits is higher). Performance on AVX2 is verified for Windows (no regressions). **Breaking Change: macOS builds** With this upgrade we are also retiring the macOS pipelines due to lack of build resources for LLVM macos/intel Conan packages. This only affects internal developer scenarios. Public developers continue to rely on vcpkg builds. commit 2927234171f8e6c960f654909f8ec0a2c19e3c54 Author: Kern Handa <[email protected]> Date: Fri Apr 7 17:20:42 2023 +0000 Merged PR 3172: Adds better support for compiling specifically for AVX2 targets * Plumb AVX2 flags to LLVM, with a block for macOS. We plan to remove official support for macOS/Intel starting from LLVM 15 due to limited build resources. * Initialize Target.HOST extensions using cpu_info * Added more AVX2 filecheck tests to catch LLVM lowering regressions before moving to LLVM 15 [MasonR] **Breaking Change**: Target.HOST no longer unconditionally enables the AVX2 extension if the underlying CPU does not support it, otherwise codegen may result in unsupported instructions. To compile for AVX2 if your host doesn't support AVX2, specify Target("<some known AVX2 model name>"). For example, `plan = schedule.create_plan(Target("Intel 6700"))` commit 6822bcb1fd222fe5b7e7292a9f7d1f35bcf1fdce Author: Denny Sun <[email protected]> Date: Thu Apr 6 21:47:01 2023 +0000 Merged PR 3203: Plumb target device info into llvm lowering llvm lowering now depends on some static complier macro to check target device info, which breaks cross compilation support. ``` // TODO: get check `TargetDeviceInfo` for the OS instead ``` ``` const int hostBitSize = 64; // TODO:: FIXME :: This assumes that the host is always 64bit // Should query the target hardware auto llvmIntTy = hostBitSize == 32 ? llvmI32Ty : llvmI64Ty; ```
microsoft · Apr 18, 2023 · 0319f5a · 0319f5a
1 parent 8affe97
commit 0319f5a
Show file tree

Hide file tree

Showing 51 changed files with 1,531 additions and 791 deletions.
diff --git a/accera/acc-gpu-runner/src/ACCGPURunnerMain.cpp b/accera/acc-gpu-runner/src/ACCGPURunnerMain.cpp
@@ -119,7 +119,7 @@ void AddMLIRVulkanRunnerPasses(PassManager& passManager)
 
     passManager.addPass(createConvertGpuLaunchFuncToVulkanLaunchFuncPass());
     passManager.addPass(accera::transforms::vulkan::createEmitVulkanWrapperPass());
-    passManager.addPass(createLowerToCFGPass());
+    passManager.addPass(createConvertSCFToCFPass());
     passManager.addPass(LLVM::createLegalizeForExportPass());
     LowerToLLVMOptions llvmOptions(passManager.getContext());
     llvmOptions.useBarePtrCallConv = false;

diff --git a/accera/acc-opt/test/commandline.mlir b/accera/acc-opt/test/commandline.mlir
@@ -8,6 +8,7 @@
 // CHECK-NEXT: affine
 // CHECK-NEXT: arith
 // CHECK-NEXT: builtin
+// CHECK-NEXT: cf
 // CHECK-NEXT: gpu
 // CHECK-NEXT: llvm
 // CHECK-NEXT: math

diff --git a/accera/acc-opt/test/vectorization.mlir b/accera/acc-opt/test/vectorization.mlir
@@ -15,7 +15,7 @@ module @test_accera_vectorization attributes {accv.target_device_features = "-av
         // mlir::affine::AffineLoadOp non-sequential
         // mlir::affine::AffineStoreOp sequential
         // mlir::affine::AffineStoreOp non-sequential
-        // mlir::SelectOp
+        // mlir::arith::SelectOp
         // mlir::arith::ShLIOp
         // mlir::arith::FPToSIOp
         // mlir::arith::ExtSIOp

diff --git a/accera/acc-translate/src/Target/Cpp/StdDialectCppPrinter.cpp b/accera/acc-translate/src/Target/Cpp/StdDialectCppPrinter.cpp
@@ -415,7 +415,7 @@ namespace cpp_printer
         return success();
     }
 
-    LogicalResult StdDialectCppPrinter::printSelectOp(SelectOp selectOp)
+    LogicalResult StdDialectCppPrinter::printSelectOp(arith::SelectOp selectOp)
     {
         if (selectOp.getNumOperands() != 3)
         {
@@ -728,7 +728,7 @@ namespace cpp_printer
         if (auto returnOp = dyn_cast<ReturnOp>(op))
             return printReturnOp(returnOp);
 
-        if (auto selectOp = dyn_cast<SelectOp>(op))
+        if (auto selectOp = dyn_cast<arith::SelectOp>(op))
             return printSelectOp(selectOp);
 
         if (auto getGlobal = dyn_cast<memref::GetGlobalOp>(op))

diff --git a/accera/acc-translate/src/Target/Cpp/StdDialectCppPrinter.h b/accera/acc-translate/src/Target/Cpp/StdDialectCppPrinter.h
@@ -83,7 +83,7 @@ namespace cpp_printer
         LogicalResult printReturnOp(ReturnOp returnOp);
 
         /// print SelectOp as ternary operator
-        LogicalResult printSelectOp(SelectOp selectOp);
+        LogicalResult printSelectOp(arith::SelectOp selectOp);
 
         /// print GetGlobalOp as a call to the global variable
         LogicalResult printGetGlobalOp(memref::GetGlobalOp getGlobalOp);

diff --git a/accera/accc/accc.py b/accera/accc/accc.py
@@ -23,6 +23,7 @@
 
 class SystemTarget(Enum):
     HOST = "host"
+    AVX2 = "avx2"
     AVX512 = "avx512"
     RPI4 = "pi4"
     RPI3 = "pi3"
@@ -116,6 +117,7 @@ def bstr(val):
         "-O3", "--march=arm", "-mcpu=arm1136jf-s", "--mtriple=armv6-linux-gnueabihf"
     ],
     SystemTarget.AVX512.value: ["-O3", "--march=x86-64", "-mcpu=skylake-avx512"],
+    SystemTarget.AVX2.value: ["-O3", "--march=x86-64", "-mcpu=skylake"],
     SystemTarget.ARM_CORTEX_M4.value: [
         "-Oz", "-mcpu=cortex-m4", "--mtriple=thumbv7em-arm-none-eabi",
     ],

diff --git a/accera/ir/include/argo/ArgoOps.td b/accera/ir/include/argo/ArgoOps.td
@@ -43,6 +43,9 @@ def Argo_YieldOp : Argo_Op<"yield", [NoSideEffect, ReturnLike, Terminator]>,
     argo.yield %f0, %f1 : f32, f32
     ```
   }];
+
+  // Indicate that the operation has a custom parser and printer method.
+  let hasCustomAssemblyFormat = 1;
 }
 
 def Argo_EntryPointOp : Argo_Op<"entry_point", [IsolatedFromAbove, FunctionOpInterface,
@@ -90,6 +93,9 @@ def Argo_EntryPointOp : Argo_Op<"entry_point", [IsolatedFromAbove, FunctionOpInt
 
   let skipDefaultBuilders = 1;
 
+  // Indicate that the operation has a custom parser and printer method.
+  let hasCustomAssemblyFormat = 1;
+
   let builders = [
     OpBuilder<(ins "StringRef":$entryName,
               "FunctionType":$type, "StringRef":$kernelName,

diff --git a/accera/ir/include/argo/ArgoStructuredOps.td b/accera/ir/include/argo/ArgoStructuredOps.td
@@ -246,6 +246,9 @@ def OpaqueOp : ArgoStructuredBase_Op<"opaque",
 
   let regions = (region AnyRegion:$region);
 
+  // Indicate that the operation has a custom parser and printer method.
+  let hasCustomAssemblyFormat = 1;
+
   let builders = [
     OpBuilder<
       (ins "ValueRange":$args, "int64_t":$argsIn, "int64_t":$argsOut,

diff --git a/accera/ir/src/IRUtil.cpp b/accera/ir/src/IRUtil.cpp
@@ -1000,14 +1000,31 @@ namespace util
 
     mlir::Operation* GetDefiningOpOrForLoop(mlir::Value val)
     {
-        if (mlir::isForInductionVar(val)) // AffineForOp
+        if (auto affineForOp = mlir::getForInductionVarOwner(val)) // AffineForOp
         {
-            return mlir::getForInductionVarOwner(val);
+            return affineForOp;
         }
         else if (auto scfForOp = mlir::scf::getForInductionVarOwner(val)) // SCFForOp
         {
             return scfForOp;
         }
+        else if (auto ivArg = val.dyn_cast<mlir::BlockArgument>())
+        {
+            auto block = ivArg.getOwner();
+            if (!block)
+            {
+                return nullptr;
+            }
+            auto parentOp = block->getParentOp();
+
+            // only handle AffineParallelOp and scf::ParallelOp, other block args such as function args should not return their associated ops
+            if (mlir::isa<mlir::AffineParallelOp>(parentOp) ||
+                mlir::isa<mlir::scf::ParallelOp>(parentOp))
+            {
+                return parentOp;
+            }
+            return nullptr;
+        }
         else // Arbitrary other op
         {
             return val.getDefiningOp();

diff --git a/accera/ir/src/argo/ArgoOps.cpp b/accera/ir/src/argo/ArgoOps.cpp
@@ -128,17 +128,17 @@ static LogicalResult verify(CopyOp op)
 // YieldOp
 //===----------------------------------------------------------------------===//
 
-static void print(OpAsmPrinter& p, argo::YieldOp op)
+void YieldOp::print(OpAsmPrinter& p)
 {
-    p << op.getOperationName();
-    if (op.getNumOperands() > 0)
-        p << ' ' << op.getOperands();
-    p.printOptionalAttrDict(op->getAttrs());
-    if (op.getNumOperands() > 0)
-        p << " : " << op.getOperandTypes();
+    p << getOperationName();
+    if (getNumOperands() > 0)
+        p << ' ' << getOperands();
+    p.printOptionalAttrDict((*this)->getAttrs());
+    if (getNumOperands() > 0)
+        p << " : " << getOperandTypes();
 }
 
-static ParseResult parseYieldOp(OpAsmParser& parser, OperationState& result)
+ParseResult YieldOp::parse(OpAsmParser& parser, OperationState& result)
 {
     SmallVector<OpAsmParser::OperandType, 2> opInfo;
     SmallVector<Type, 2> types;
@@ -243,33 +243,33 @@ void OpaqueOp::build(
     bodyBuild(odsBuilder, odsState.location, bodyBlock->getArguments());
 }
 
-static void print(OpAsmPrinter& p, OpaqueOp op)
+void OpaqueOp::print(OpAsmPrinter& p)
 {
-    auto attrNames = op.argoTraitAttrNames();
+    auto attrNames = argoTraitAttrNames();
     llvm::StringSet<> argoTraitAttrsSet;
     argoTraitAttrsSet.insert(attrNames.begin(), attrNames.end());
     SmallVector<NamedAttribute, 8> attrs;
-    for (auto attr : op->getAttrs())
+    for (auto attr : (*this)->getAttrs())
         if (argoTraitAttrsSet.count(attr.getName().strref()) > 0)
             attrs.push_back(attr);
 
-    auto dictAttr = DictionaryAttr::get(op.getContext(), attrs);
-    p << op.getOperationName() << " " << dictAttr;
-    p.printOptionalAttrDict(op->getAttrs(), attrNames);
-    p << " (" << op.getOperands() << ")";
-    if (!op.region().empty())
+    auto dictAttr = DictionaryAttr::get(getContext(), attrs);
+    p << getOperationName() << " " << dictAttr;
+    p.printOptionalAttrDict((*this)->getAttrs(), attrNames);
+    p << " (" << getOperands() << ")";
+    if (!region().empty())
     {
-        p.printRegion(op.region());
+        p.printRegion(region());
     }
 
-    auto inputTypes = op.getOperandTypes();
+    auto inputTypes = getOperandTypes();
     if (!inputTypes.empty())
     {
         p << " : " << inputTypes;
     }
 }
 
-static ParseResult parseOpaqueOp(OpAsmParser& parser, OperationState& result)
+ParseResult OpaqueOp::parse(OpAsmParser& parser, OperationState& result)
 {
     SmallVector<OpAsmParser::OperandType, 8> operandsInfo, regionOperandsInfo;
     DictionaryAttr dictAttr;
@@ -340,8 +340,8 @@ void EntryPointOp::build(OpBuilder& builder, OperationState& result, StringRef e
 /// Parse an Argo entry_point op
 /// <operation> ::= `argo.entry_point` symbol-ref-id `(` argument-list `)`
 ///                 (`->` function-result-list)? function-attributes?
-static ParseResult parseEntryPointOp(OpAsmParser& parser,
-                                     OperationState& result)
+ParseResult EntryPointOp::parse(OpAsmParser& parser,
+                                OperationState& result)
 {
     SmallVector<OpAsmParser::OperandType, 8> entryArgs;
     SmallVector<Type, 8> argTypes;
@@ -387,17 +387,17 @@ static ParseResult parseEntryPointOp(OpAsmParser& parser,
     return success();
 }
 
-static void printEntryPointOp(OpAsmPrinter& p, EntryPointOp op)
+void EntryPointOp::print(OpAsmPrinter& p)
 {
     p << EntryPointOp::getOperationName() << ' ';
-    p.printSymbolName(op.getName());
+    p.printSymbolName(getName());
 
-    FunctionType type = op.getType();
-    function_interface_impl::printFunctionSignature(p, op.getOperation(), type.getInputs(),
-                                               /*isVariadic=*/false,
-                                               type.getResults());
+    FunctionType type = getType();
+    function_interface_impl::printFunctionSignature(p, getOperation(), type.getInputs(),
+                                                    /*isVariadic=*/false,
+                                                    type.getResults());
 
-    function_interface_impl::printFunctionAttributes(p, op.getOperation(), type.getNumInputs(), type.getNumResults());
+    function_interface_impl::printFunctionAttributes(p, getOperation(), type.getNumInputs(), type.getNumResults());
 }
 
 static LogicalResult verify(EntryPointOp op)

diff --git a/accera/ir/test/nest_dialect_test/IRTestVerification.cpp b/accera/ir/test/nest_dialect_test/IRTestVerification.cpp
@@ -16,6 +16,7 @@
 #include <ir/include/nest/Range.h>
 #include <ir/include/nest/TransformedDomain.h>
 
+#include <value/include/TargetDevice.h>
 #include <transforms/include/nest/LoopNestPasses.h>
 #include <transforms/include/value/ValueToLLVMLoweringPass.h>
 #include <transforms/include/value/ValueToStandardLoweringPass.h>
@@ -376,7 +377,7 @@ bool VerifyLowerToLLVM(mlir::OwningOpRef<mlir::ModuleOp>& module, mlir::FuncOp&
 
             funcPm.addPass(mlir::arith::createArithmeticExpandOpsPass()); //  --arith-expand 
             pm.addPass(mlir::createLowerAffinePass());  //  --lower-affine 
-            pm.addPass(mlir::createLowerToCFGPass());  //  --convert-scf-to-std 
+            pm.addPass(mlir::createConvertSCFToCFPass());  //  --convert-scf-to-cf 
             pm.addPass(mlir::createMemRefToLLVMPass());  //  --convert-memref-to-llvm 
             pm.addPass(mlir::createLowerToLLVMPass());  //  --convert-std-to-llvm="use-bare-ptr-memref-call-conv" 
             pm.addPass(mlir::createConvertVectorToLLVMPass());  //  --convert-vector-to-llvm
@@ -437,7 +438,7 @@ bool VerifyTranslateToLLVMIR(mlir::OwningOpRef<mlir::ModuleOp>& module, mlir::Fu
 
             funcPm.addPass(mlir::arith::createArithmeticExpandOpsPass()); //  --arith-expand 
             pm.addPass(mlir::createLowerAffinePass());  // --lower-affine 
-            pm.addPass(mlir::createLowerToCFGPass());  //   --convert-scf-to-std 
+            pm.addPass(mlir::createConvertSCFToCFPass());  //   --convert-scf-to-cf 
             pm.addPass(mlir::createMemRefToLLVMPass());  //   --convert-memref-to-llvm 
             pm.addPass(mlir::createLowerToLLVMPass());  //   --convert-std-to-llvm="use-bare-ptr-memref-call-conv" 
             pm.addPass(mlir::createConvertVectorToLLVMPass());  //  --convert-vector-to-llvm